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APU Floating-Point Unit v3.1

If you have enabled profiling (by defining the symbol PROFILING in the profile.h file), a summary of execution time is shown at the end of each demo. All figures are in PowerPC clock cycles.

Example Design Source Files

Table 5 gives an overview of the source code files included with the ML403 demonstration project, along with a brief description of the contents of each file.

Table 5: Source code files included with example design

File(s) demos.h mand.c fig.c gaussian.c metropolis.c fourierf.c qrand.c, qrand.h ttygfx.c, ttygfx.h uartio.c, uartio.h profile.c, profile.h xmath.h

Description Prototypes and configuration definitions for demo functions Draws the Mandelbrot set Draws Feigenbaum’s "fig-tree" fractal Demonstrates the generation of normally-distributed random numbers Solves the Traveling Salesman problem by simulated annealing Performs 64-point Fast Fourier Transforms Random number generation Graphics display on an RS232 ANSI terminal Handles UART input without the overhead of the C standard library Utilities for measuring execution times Wrapper around standard math.h include

TestApp_Memory.c

Top level demo application

Resource Utilization and Performance

Table 6 shows silicon resource utilization figures for the various supported FPU configurations. Note that the presence of any fabric co-processor on the APU interface causes the maximum operating fre- quency of the PowerPC processor to drop. See latest Virtex-4 FX datasheet for exact figures. When the FPU is connected to the APU interface of a PowerPC core through the FCB, operation is possible at up to a 233 MHz FCB clock frequency (-10 part).

Table 6: Resource Usage of Floating-Point Unit (approximate) Resource Usage

Coprocessor Variant

Slices

Xtreme-DSP blocks

Block RAMs

Lite (no div/sqrt)

1300

4

2

Full (with div/sqrt)

1600

4

2

Note that minor variations in maximum operating frequencies and slice counts may be seen between different versions of Xilinx implementation tools. Higher performance may be achievable by altering the mapping and/or place and route options, or by selecting a device with a faster speed grade. Remember that the run-time of the implementation tools can often be improved by providing a suffi- cient timing margin.

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www.xilinx.com

March 11, 2008 Product Specification

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