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APU Floating-Point Unit v3.1

References

[1] PowerPC™ 405 Processor Block Reference Guide (v2.0); August 20, 2004; Xilinx ref. UG018 [2] Book E: Enhanced PowerPC™ Architecture Version 1.0; May 7, 2002; IBM Corporation [3] Computer Architecture: A Quantitative Approach; 2nd Ed, 1996; J. L. Hennessy & D. A. Patterson

Revision History

Date 3/21/05 9/23/05 1/26/06 2/13/06 5/1/06 6/21/06 1/26/07 3/11/08

Version 1.0 1.1 1.2 1.3 2.0 2.5 3.0 3.1

Revision

Provisional Xilinx release Updated for version 1.1 of FPU hardware Updated for version 2.0 of FPU hardware Corrected instruction support and size information Document updated for early release v2.0 Updated for v2.1 release. Updated for v3.0 release. Updated for v3.1 release.

March 11, 2008 Product Specification

www.xilinx.com

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