APU Floating-Point Unit v3.1

# Functional Overview

The APU Floating-Point Unit comprises a number of execution units, a register file, bus interface and all the control logic necessary to manage the execution of floating-point instructions. Figure 1 provides an overview of the FPU architecture.

### Figure Top x-ref 1

Execution

Mov, Abs, Neg

Control /

Decode Logic

Add/Subtract

Multiply

Register

Divide

File

Square Root

FCB Bus

FCB Bus Interface

Figure 1: Top-level APU Floating-Point Coprocessor Architecture

# Applications

The APU Floating-Point Unit augments the capabilities of the PowerPC 405 processor core with sup- port for floating-point instructions. Many software applications make use of floating-point (or real) arithmetic, whether for occasional calculations or for intensive computation kernels. Following are some examples of application areas where floating-point arithmetic can be useful.

is needed to retain fidelity.

and radar where algorithms such as QR Decomposition and Singular Value Decomposition are numerically unstable without sufficient dynamic range.

tion errors can lead to sub-optimal results.

data samples may be difficult to predict at design time.

ad hoc calculations, where floating-point is often the simplest way to avoid integer overflow and rounding errors.

## Increased Processing Capacity

The APU Floating-Point Unit increases the processing capacity of a PowerPC-based embedded system in the following three ways:

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March 11, 2008 Product Specification