APU Floating-Point Unit v3.1
Hardware floating-point operations complete faster than the equivalent software emulation routines, making floating-point arithmetic faster.
In software, only one floating-point operation can be in progress at a time. The floating-point operators within the FPU are pipelined so that multiple floating-point calculations can proceed in parallel. This parallelism in a floating-point algorithm can lead to dramatic speedups.
The FPU is autonomous; therefore, the PowerPC internal pipeline can continue to execute integer operations.
Figure 2 illustrates a typical embedded system containing an APU Floating-Point Unit.
Figure Top x-ref 2
APU Floating Point Unit
Virtex−4 PowerPC Block
Other peripherals in system (e.g. RAM, UART, EMAC)
Figure 2: Embedded System Containing an APU-FPU Core
The Register file contains 32 floating-point registers. The width of these registers is 32 bits (single pre- cision). The APU/FCM interface ports are also 32 bits wide.
The APU/FCM interface between the Floating-Point Coprocessor and the PowerPC 405 core is described in detail in the PowerPC 405 Processor Block Reference Guide (reference 1 in this document).
PowerPC Instruction Set Support
The FPU supports two operator configurations (full and lite). Table 1 details which instructions are sup- ported by each configuration. For more information about the PowerPC floating-point instruction set, see Book E: Enhanced Power PC Architecture Version 1.0, (reference 2).
In the full configuration, the addition, subtraction, multiplication, division, and square root operations are supported, along with fused multiply-add and its sign-modified variants. The lite mode is similar, but divide and square root operators are not included. The reciprocal estimate and reciprocal square root estimate functions are not supported in either configuration.
March 11, 2008 Product Specification