APU Floating-Point Unit v3.1
Table 1: PowerPC FP Instruction Set Support (Continued)
mtfsb0 mtfsb1 mtfsf mtfsfi
Move to status/control register bit 0 Move to status/control register bit 1 Move to status/control register fields Move to status/control register immediate
Key: Yes = supported; No = not supported; SP = operation performed in single-precision; NS = non-standard (see note)
1. The FPU will treat the fcfid (convert from signed integer double-word to FP double) as if it were fcfiw (convert from signed integer word to FP single). This behaviour is non-standard, but allows hardware acceleration of format conversions that would not otherwise be pos- sible in a single-precision unit.
The "dotted" instruction forms, which return exception summary information to PowerPC condition register 1 on completion, are not supported in any configuration.
If a program attempts to execute an unsupported floating-point instruction, there are two possible out- comes. If the instruction belongs to one of the groups that can be disabled by the APU controller and this group has been disabled, then an exception will be raised. Otherwise, the result is boundedly unde- fined. Use the appropriate compiler flags to ensure that unsupported instructions are not generated by the compiler. See the Xilinx PowerPC GNU Compiler Reference Manual for details.
IEEE 754-1985 Standard Compliance
The Floating-Point Unit complies with the IEEE-754 standard for binary floating-point arithmetic, with the following exceptions.
Rounding Modes. Except for those instructions that explicitly round their result towards zero, the only supported rounding mode is round-to-nearest (the default in IEEE-754). An attempt to configure the FPU to operate in any other rounding mode will have no effect.
Denormalized Numbers. The standard defines a means of representing very small numbers by allowing significands of the form "0.x" in addition to the usual “1.x” of normalized floating-point
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unrepresentable. If an operation produces such a value, the FPU will indicate an arithmetic underflow. If an operation is presented with such a value, it will be treated as if that value were an
Double-on-Single. The FPU accepts and executes double-precision arithmetic operations using the single-precision hardware operators. The fadd and fadds instructions are indistinguishable.
Floating-Point Status and Control Register
The Floating-Point Status and Control Register (FPSCR) is implemented as described in the PowerPC Book-E specification (reference 2). All instructions for explicit access to this register are supported except for mcrfs (that is: mffs, mtfsb0, mtfsb1, mtfsf and mtfsfi). All FPSCR instructions (other than mffs) take approximately 36 FCB clock cycles to execute.
The following lists some minor deviations from the Book-E-specified behavior. They are mostly con- cerned with exactly how the FPSCR bits are set as a by-product of executing arithmetic instructions.
Bit 38 - Inexact exception. Always reads as zero. Bit 39 - Invalid operation (Signalling NaN). All NaNs are currently treated as Quiet NaNs. This bit
March 11, 2008 Product Specification