X hits on this document

32 views

0 shares

0 downloads

0 comments

6 / 17

APU Floating-Point Unit v3.1

always reads as zero. Bit 44 - Invalid compare exception. Always reads as zero. Bit 45 - Fraction Rounded. This bit always reads as zero. Bit 46 - Fraction Inexact. This bit always reads as zero. Bits 48-51 - Result flags. These bits are not set by compare operations. Bit 61 - non-IEEE mode. This bit is ignored. Only IEEE mode is supported.

Bits 62:63 - Rounding Control. Round-to-Nearest mode is always used; setting these bits has no effect.

The only Floating-Point exception modes currently supported is “exceptions ignored” mode.

Adding an FPU to an EDK Project

As of EDK 9.1i the Base System Builder wizard allows the APU FPU to be included in a project by means of a simple check-box in the PowerPC configuration dialog. Provided that the clocking architec- ture that was chosen is compatible with the FPU, the wizard will automatically add the FPU and FCB cores and make the appropriate connections between them. The only requirement is that the system (bus) clock be running at half the frequency of the processor clock.

If there is no half-rate clock, or it is necessary to add the APU FPU to an existing PowerPC-based EDK project, then two basic steps are required. These steps are described in more detail in this section.

  • 1.

    Add the FPU and the associated Fabric Coprocessor Bus (FCB) interface to the project.

  • 2.

    Wire up the appropriate clock and reset signals to ensure correct FCB/FPU operation.

There are two clock domains in a PowerPC-FPU system—the PowerPC (core) clock and the FPU clock. The FPU logic runs internally at half the speed of the PowerPC. The FCB interface must utilize the same clock as the PowerPC (i.e. a 1:1 ratio). If your project does not already have a suitable clock signal for the FPU’s internal half-rate clock, consult the platform studio documentation for how to add an appro- priate DCM module, or modify an existing one to produce an appropriate clock signal. Details of the achievable clock speeds for the FPU can be found in the LogiCORE Facts table on page 1.

To quickly get started using the FPU, use the example EDK project from the reference design provided as a starting point. The ML403 reference design supplied with the FPU is configured with the PowerPC at 200 MHz, and the FPU and system logic at 100 MHz. For more information, see "Example Design Source Files" on page 16.

Using the FPU in EDK

This section contains the procedure for adding the FPU to an EDK project. The steps illustrated are for EDK v9.1i, but the general procedure also applies to later versions of EDK.

Adding FPU and FCB Cores

  • 1.

    Click the IP catalog tab on the Platform Studio window. The apu_fpu core appears under the arithmetic category.

  • 2.

    Double-click apu_fpu to add the FPU to your project. The fcb_v1_0 core appears under the bus category.

  • 3.

    Double-click fcb_v1_0 to add the FCB bus to your project.

  • 4.

    Go to the System Assembly view and select Bus Interface from the Filters radio selector at the top of the page.

6

www.xilinx.com

March 11, 2008 Product Specification

Document info
Document views32
Page views32
Page last viewedSat Dec 03 01:04:34 UTC 2016
Pages17
Paragraphs560
Words6171

Comments