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APU Floating-Point Unit v3.1

The FCB appears as a bus connecting the PowerPC-405 core (master) to the APU FPU core (slave).

  • 5.

    Expand these two instances to reveal the MFCB and SFCB interfaces inside.

  • 6.

    Click on the empty square and the empty triangle on the FCB bus line to connect the master and

slave interfaces together. An example of a correct FCB configuration is shown in Figure 3.

Figure Top x-ref 3

Figure 3: FCB Bus Connection Between PowerPC and APU-FPU

  • 7.

    Right-click the FPU instance in the System Assembly view, and select Configure IP.

  • 8.

    Set the feature-set of the FPU according to your requirements.

  • 9.

    Right-click the PowerPC CPU instance in the System Assembly view, and select Configure IP.

  • 10.

    Click the tab marked APU, and modify the APU Controller Configuration Register Initial Value to

0b0000000000000001 to enable the APU interface. Wiring the FCB Clock Signals

The example in this section assumes that the PowerPC core is using a clock called PROC_CLK_S, and the FCB is running at half this frequency, using a clock called SYS_CLK_S. These are the default system clock names provided by the Base System Builder tool. You can replace these names with the appropri- ate clock signals in your system.

  • 1.

    Go to the System Assembly view and select the Ports filter.

  • 2.

    Expand the FCB instance to see its ports.

  • 3.

    To specify the signal connected to a port, select the port and click in the Net column, then select or type the name of the appropriate signal name. If desired, you can create a new internal signal by typing a name that does not currently exist within the system.

  • 4.

    The FCB_CLK port must be connected to the PowerPC processor clock (PROC_CLK_S in this example). The SYS_RST port must be connected to the system reset net, usually called SYS_BUS_RESET.

  • 5.

    Now expand the FPU instance to see its ports.

  • 6.

    The FCB_CLK port must be connected to the PowerPC processor clock (PROC_CLK_S in this example). The FPU_CLK port must be connected to the half-rate clock (SYS_CLK_S in this example).

March 11, 2008 Product Specification

www.xilinx.com

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