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folders” would have been handy. However, designers tend to develop an intuitive feeling for “how Modelsim thinks” that is of that typical tacit knowledge type that engineers are so well known for possessing. (Knowledge that “reside in the fingers of the tool operator” and does not appear in the tool manuals.)

The project would then successfully run through an exhaustive post-simulation test suite, testing all buttons and text output in a very long, automated script that would run for about 5 hours on an ordinary Sun workstation.


Place and Route

During place and route the design was imported into the Cadence chip design tool called Silicon Ensemble. The Verilog description file generated from the synthesis step was used at

this final design. The chip floor area had to be extended from the preset defaults to 2100

2100 square

microns in order to fit the RAM memory. The suggested values from the scripts delivered with our SE setup would not fit it. The RAM memory proved complicated to place using a script and had to be placed by hand. The block halo had to be increased to 55 microns in order to avoid power net routing constraint violations.

One of the first problems during place and route was that signals had been added to the top component in order to support writing of flash memory contents. An 8-bit write data bus and three chip control signals had been added. This path was incorrect, since the data bus for the flash memory is bidirectional (tristate) and thus it would have been necessary to introduce logic to switch the control pads for the data bus from read to write.

While this was indeed possible, it would have introduced delays in the project and in- creased the risk of a failed design, so the design team opted to disconnect the flash write functionality, so that the topmost component would resemble that of other project teams, and make it pin-compatible with their designs. This makes it possible, among other things, to use the same physical testbench at chip verification.

The logic for flash write and firmware upload was left in the VHDL model so that it may be reactivated: only the topmost signals (on controller_top) were removed.

One small additional problem occurred when performing place and route: the command ctgentool complained about a piece of code that inverted the clk signal and passed it imme- diately to the SPI sclk signal.

The lesson learned is that one can never actually use the clk signal in constructions; one should only use it for triggering logic functions with rising_edge(clk) constructs. This way it proved wise to implement a true halt function in the IP-component: had this not been done, the clocknet routing would probably have ended up all wrong.

The final chip design has the look of figure 2.


Fabrication and testing

After finalizing design, our chip was manufactured and we ran a test of functionality. A (physical) testbench was built at the ASIC department and used for all chips in this project run. The testbench had the LCD, DAC and MP3 decoder chip in place and interfaced to the controller using a socket which had pins connected according to the pin layout of the project files. The push-buttons on the testbench were decoupled to avoid jitter.


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