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The construction principle of using a CPU IP-core and construct peripheral components around an MMU proved feasible, though complex. However the final design exhibits a fu- ture flexibility that would not have been possible using state machine constructs only. Using the off-the-shelf Free6502 IP-core was simple and the only modification done was to intro- duce a “halt” signal to the CPU.

Creating firmware for the CPU proved to be very simple. Any experienced assembler programmer can easily set up the development tools. One very good thing about using upgradable firmware is that while the chip has already been sent to production, firmware can still be developed and the final user interface design is not fixed. Adding e.g. graphic equalizer capabilities and volume control to the firmware is still possible.

The PC connection bus was implemented for firmware uploads, but since the memory write capability was removed, the original purpose is no longer feasible. Yet, the port may be utilised by firmware to carry out e.g. remote control or file streaming.

Interfacing the memory-mapped I/O, Flash and RAM memory to the CPU proved very complicated. The lesson learned is that MMU:s are complex creatures.

Using a CPU consumed a lot of silicon space. The on-chip RAM memory for the system stack, zeropage and user RAM also consumed a lot of space. However: using an arithmetic- only CPU simultaneously saved space on the chip as complicated operations such as multi- plication could be implemented by way of arithmetic software.

The success with manufacturing of this chip give at hand that the design decisions made were correct, but that running a CPU off flash memory will cost something in terms of power dissipation.


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