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2.3

D C U RT

The DAC UART is another simple memory-mapped I/O component that serialise data and send it to the DAC. It is currently only used for initialisation once during startup, but the dynamic firmware structure makes it possible to add firmware that lets the user customise the DAC settings. (See below on firmware.)

The DAC actually has a 7-bit address and 9-bit data bus combined into a 16 bit word, but during implementation it was see as a single 16-bit word for the sake of simplicity. The firmware is supposed to re-implement and understand the true nature of the 7+9 data format in the 16 bits transfered to the DAC by way of the DAC UART.

2.4

MP3 U RT

This component request bytes from the flash memory (by way of the memory manage- ment unit) and serialise them in a format suiting the MP3 chip that was to be used in this project. It is not controlled directly by the processor–rather the memory management unit controls DMA-like registers that will independently stream data to the MP3 UART.

The MP3 UART is actually a subcomponent of the MMU (see below) and is thus not visible directly inside the topmost controller component.

2.5

MMU

The MMU (memory management unit) has a central role and is, apart from the Free6502 processor core, the most advanced component in our construction.

This unit maps request for addresseses both in Flash ROM, RAM and the memory port area. It handles CPU stall cycles introduced due to the slowness of the Flash, RAM synchro- nisation, and mapping of hardware ports into processor address space.

Further, the MMU contains a small DMA controller that will stream data from the Flash ROM to the MP3 chip, introducing stall cycles to the CPU if both try to access the Flash at the same time. The UART serialisation to the MP3 chip is carried out by a subcomponent called MP3UART (see above).

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