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The MMU also controls the reset of the MP3 chip when ”stop” or ”pause” states are ac- tive. Such requests will generate a reset signal to the MP3 chip in order to silence any PCM remnants in the ring buffers.

It also presents registers to control this DMA transfer to the processor, and registers which make it possible to write bytes to the Flash PROM on user request. However, they user must first erase the chip with a special erase command. When this command has commenced, bytes may be written to the PROM.

The erase command will erase the entire PROM, so it is necessary to download both firmware and all MP3 songs after erasing the memory.

During Flash memory writing, the processor will of course be stalled from reading the Flash memory so that two accesses does not collide. However it is assumed that when writing to the Flash, no MP3 playing is taking place at the same time. As firmware upload can only commence at system startup, this should not be a problem.

This write functionality was however removed during final place and route. Also see the subsection on memory layout below.


On the Free6502 processor

Free6502 is (like its parent) an 8-bit CPU. It features only arithmetic: operations like mul- tiplication and division must be programmatically constructed. This has the downside of complicating program development (though stock subroutines for e.g. floating point may be easily employed) but on the other hand, the strictly arithmetic nature of the unit ensures a very simple and compact piece of VHDL code, which will synthesize to form a small physical footprint.

The CPU has one general-purpose 8-bit register (the accumulator), and four special- purpose registers: two index registers named X and Y (both 8-bit), an 8-bit stack pointer (producing a stack of 256 bytes) and a 16-bit program counter. There is also a state register for things like carry, overflow, zero result e.t.c., no more than 8 additional bits.

The Free6502 processor was easy to use and add to the project. It consists of two VHDL files named free6502.vhd and microcode.vhd. The latter file, as the name suggests, contains the microcode that make up the actual instruction set of the processor. The processor compiled fine immediately after adding these two files to the project VHDL repository.

The 6502 will assert memory addresses on the address bus and expects the contents of the memory address to be available (or written to) that memory address in one clock cycle. In difference from the quite common physical 6502 component, the Free6502 features separate input- and output- data buses. Commonplace microprocessors use bidirectional buses to decrease pin count, but inside a SoC this is not an issue.

At power-on, a RESET signal is asserted to the Free6502 component. The component will then assert the memory addresses $FFFC6 and $FFFD for reading, yielding a 16-bit memory address from these two bytes. The program counter (PC) will then be set to this address, where a bootstrap startup sequence begins.

Certain difficulties arise when devising the memory management unit, but this will be treated in more depth in the following subsection.

6The addresses in this paper are given in hexadecimal notation.


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