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Memory layout

The first construction used 32 KB on-chip SRAM memory and a 4KB PROM for the proces- sor. This enabled the processor to fetch data from the SRAM memory at each rising clock cycle. The interface to the Flash memory was asynchronous, so the processor would request a location in Flash through an I/O memory port and then wait for it to appear on another port. The memory layout was this:

$0000-$00FF

Zeropage

$0100-$01FF

Stack

$0200-$7FFF

Work RAM

$8000-$80FF

I/O Ports

$F000-$FFFF

PROM

This design was doomed when it was discovered that the on-chip SRAM memories avail- able to us were limited to 1 KB (i.e. $0400 bytes).

The memory design was then refactored by connecting the Flash RAM to the system address bus, and allowing the first 64 KB of the Flash to be utilised as processor ROM. This also simplified the handling of firmware upgrades (which were previously planned to be accomplished by uploading chunks of memory from flash to the on-chip SRAM, and starting the program there) as everything could be read on-the-fly from the Flash ROM.

The new memory layout was the following:

$0000-$00FF

Zeropage

$0100-$01FF

Processor stack

$0200-$03FF

Work RAM

$0400-$7FFF

PROM

$8000-$83FF

I/O Ports

$8400-$FFFF

PROM

There was however a problem: accessing the Flash RAM was slower than one clock cycle (at which time the CPU expected requests on the address bus to be valid on it’s data in lines).

This problem was solved by lining the CPU clock line through the MMU unit, so that the MMU would force the CPU clock line low when it was busy accessing requested data. This would inhibit the CPU when accesses were going on, and was much better than sim- ply reducing the CPU frequency: the CPU speed would only be reduced when absolutely necessary.

It was however indicated that this clock-inhibiting approach could have a negative im- pact on the routing of the clock nets of the finished circuit, so as a further design iteration step, a true “hold” signal was added to the Free6502 component during synthesis work. This worked out fine.

The first 64 KB of the Flash memory were used, but the SRAM at $0000-$03FF and the I/O ports at $8000-$83FF disabled 2 KB of that memory. The SRAM and the ports “overlay” the RAM memory, so that the CPU can’t “see it”. Of course the C programs supplied as input to the project and intended to generate the contents of the flash memory also had to be rewritten accordingly.

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