Further, the RAM and ROM memory type expected from the CPU was to be asynchronous, i.e. putting an address value on it’s address pins would immediately read (or write, if the WE pin was high) that memory address, and not wait for a clock pulse to pass. The example ROM that came with the model was coded in this manner:
when "000000000000" =>
data <= "10100010";
-- 0 = A2
when "000000000001" =>
data <= "11111111";
-- 1 = FF
when "000000000010" =>
data <= "10011010";
-- 2 = 9A
when "000000000011" =>
data <= "00100000";
-- 3 = 20
architecture FOO of rom is begin process (addr) begin case addr(11 downto 0) is
When it came to generating memories for inclusion in the project, only synchronous RAM was available, resulting in two possible scenarios for interfacing to the CPU: generate an asynchronous RAM memory or hold the CPU for one cycle, so that requested addresses will be clocked in to the synchronous RAM. The latter approach was chosen, so that the CPU is inhibited for one clock cycle when reading from RAM, and for several clock cycles when reading from the Flash.
The firmware for the CPU was written in pure 6502 assembler using the DASM assembler,7 originally intended for writing programs for the Atari 2600 computer.
Getting this assembler to compile on Solaris was troublesome but it proved possible with some C hacking. After that it would compile programs without any problems.
The asm subdirectory of the project contain raw assembler code (mp3rom.asm) as used by the processor. Here, one can also find the Free6502 authors idea of a ROM VHDL represen- tation of the same program (mp3rom.vhd). However the design do not use this VHDL-file: instead the object code is linked by a modified version of the TOC building C program build- toc.c, which is found in the c subdirectory.
The assembler file contains all port definitions and similar things needed to write firmware for the controller, and may be compiled by issuing a “gmake” command in the directory, which will compile the code by way of GNU Make. Subsequently entering the c subdirectory and executing “gmake toc” will create the raw Flash image to be programmed to the Flash PROM.
If both buttons ”play” and ”stop” are held down when the controller is powered up (at reset), the controller will enter firmware upload mode and start a receiving program that listens for a 115.2 kbps connection on the PC I/O port.
To handle firmware upgrades in this architecture, the PROM sets up the transfer and then copies a small recieveing program to RAM address $0200 and starts it there. This enables the processor to overwrite $0400-$7FFF and $8400-$FFFF without interfering with it’s own code.