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NXP Semiconductors

Product specification

Economy audio CODEC for MiniDisc (MD) home stereo and portable applications

UDA1341TS

7.21.1 Table 6

STATUS CONTROL Data transfer of type ‘STATUS’

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

0

RST

SC1

SC0

IF2

IF1

IF0

DC

1

OGS

IGS

PAD

PDA

DS

PC1

PC0

REGISTER SELECTED

RST = reset SC = system clock frequency (2 bits) IF = data input format (3 bits) DC = DC-filter OGS = output gain (6 dB) switch IGS = input gain (6 dB) switch PAD = polarity of ADC PDA = polarity of DAC DS = double speed PC = power control (2 bits)

7.21.1.1 Reset

7.21.1.4

Data input format

A 1-bit value to initialize the L3-registers with the default settings except system clock frequency.

A 3-bit value to select the data input format.

Table 7

Reset settings

RST

0 1

no reset reset

FUNCTION

7.21.1.2

System clock frequency

A 2-bit value to select the used external clock frequency.

0

0

512fs

0

1

s 384f

1

0

s 256f

1

1

not used

Table 8

System clock settings

SC1 SC0

FUNCTION

0 0 0 0 1

0 0 1 1 0

0 1 0 1 0

I2S-bus LSB-justified 16 bits LSB-justified 18 bits LSB-justified 20 bits MSB-justified

1

0

1

LSB-justified 16 bits input and MSB-justified output

1

1

0

LSB-justified 18 bits input and MSB-justified output

1

1

1

LSB-justified 20 bits input and MSB-justified output

Table 10 Data input format settings

IF2 IF1

IF0

FUNCTION

7.21.1.3 DC-filter A 1-bit value to enable the digital DC-filter.

DC

0

no DC-filtering

1

DC-filtering

Table 9

DC-filtering settings

FUNCTION

2002 May 16

15

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