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SYMBOL

PIN

DESCRIPTION

L3DATA BCK WS DATAO DATAI TEST1 TEST2 AGCSTAT QMUTE VOUTR V VOUTL VSSA(DAC) V

DDA(DAC)

ref

15 16 17 18 19 20 21 22 23 24 25 26 27 28

L3-bus data input and output bit clock input word select input data output data input test control 1 (pull-down) test control 2 (pull-down) AGC status quick mute input DAC output right DAC analog supply voltage DAC output left DAC analog ground ADC and DAC reference voltage

SYMBOL

PIN

DESCRIPTION

V VINL1 V VINR1 VADCN VINL2 V VINR2 OVERFL V V SYSCLK L3MODE L3CLOCK

SSA(ADC)

DDA(ADC)

ADCP

DDD

SSD

1 2 3 4 5 6 7 8 9 10 11 12 13 14

ADC analog ground ADC1 input left ADC analog supply voltage ADC1 input right ADC negative reference voltage ADC2 input left ADC positive reference voltage ADC2 input right decimation filter overflow output digital supply voltage digital ground system clock 256fs, 384fs or 512fs L3-bus mode input L3-bus clock input

NXP Semiconductors

Product specification

UDA1341TS

Economy audio CODEC for MiniDisc (MD) home stereo and portable applications

6

PINNING

VSSA(ADC) handbook, halfpage

1

VINL1

2

DDA(ADC)

3

VINR1

4

VADCN

5

V

28

Vref

27

VSSA(DAC)

26

VOUTL

25

VDDA(DAC)

24

VOUTR

VSSA(ADC) handbook, halfpage

1

VINL1

2

DDA(ADC)

3

VINR1

4

VADCN

5

V

28

Vref

27

VSSA(DAC)

26

VOUTL

25

VDDA(DAC)

24

VOUTR

VINL2

6

VADCP

7

VINR2

8

23

QMUTE

22

AGCSTAT

21

TEST2

UDA1341TS

VINL2

6

VADCP

7

VINR2

8

23

QMUTE

22

AGCSTAT

21

TEST2

UDA1341TS

OVERFL

9

VDDD

10

VSSD

11

SYSCLK

12

L3MODE

13

20

TEST1

19

DATAI

18

DATAO

17

WS

16

BCK

OVERFL

9

VDDD

10

VSSD

11

SYSCLK

12

L3MODE

13

20

TEST1

19

DATAI

18

DATAO

17

WS

16

BCK

L3CLOCK 14

15 L3DATA

L3CLOCK 14

15 L3DATA

MGR428

MGR429

Marked pins are compatible with UDA1340M

Fig.2 Pin configuration.

Fig.3 Compatible pins with UDA1340M.

2002 May 16

6

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