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Texas Instruments

Reset_N

XOSC_Q2 XOSC_Q1

P2_4 P2_3 P2_2 P2_1 P2_0

P1_7 P1_6 P1_5 P1_4 P1_3 P1_2 P1_1 P1_0

P0_7 P0_6 P0_5 P0_4

P0_3 P0_2

P0_1 P0_0

I/O Controller

SRF bus

SRF bus

SYNTH

Receive

Frequency synthesizer

Transmit

FIFO and frame control

AES encryption

Radio registers

ADC Audio/DC

and decryption

CSMA/CA strobe processor

Radio data interface

Digital

RAM

8-KB SRAM

FLASH

32-/64-/128-/256- KB FLASH

FLASH CTRL

Debug Interface

8051 CPU Core

DMA

IRQ CTRL

High speed

32- kHz

RC-OSC

RC-OSC

Reset

Wathdog timer

Clock MUX and calibration

Sleep timer

PDATA

XRAM IRAM

SFR

Unified

Memory arbitrator

USART 0

USART 1

Timer 1 (16-bit)

Timer 2 (IEEE 802.15.4 MAC timer)

RF_P

RF_N

Power management controller

On-chip voltage

VDD (2.0 - 3.6 V)

regulator

DCOUP

32-MHz Crystal OSC

32.768-kHz Crystal OSC

Demodulator and AGC

Modulator

Timer 3 (8-bit)

Power on reset brown out

Timer 4 (8-bit)

Analog

Mixed

Figure 6: CC2530 ZigBee system-on-chip block diagram

USB Both AM media and low-power processors integrate a USB host capable of supporting as many as three clients. TI will offer code for the PHDC profiles to interested customers. The PHDC profile, shown in Figure 7, is an essential component of the Continua stack. Required IEEE-11073 layers can be implemented by working with partners such as S3 or Lamprey Networks.

Medical application

Device specializations

IEEE 11073-104xx

Data exchange protocol

IEEE 11073-20601

USB API

PHDC

Physical layer

Figure 7 : Medical device profile Aggregation managers for the connected health system

CDC

HID

MSD

July 2010

7

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