X hits on this document





1 / 12

March 1998

Application Note 42045

ML4824, A Novel Method for an Off-Line PFC-PWM Combo Controller


One of the most ndesirable phenomena experienced by

tility companies is the high harmonic content of the line c rrent. The harmonic content of this line c rrent tends to ca se transformer overheating at the s bstations, which are responsible for providing power to all sectors of a given area. For three-phase distrib tion, ne tral c rrents will flow in the presence of these harmonics. For single- phase distrib tion, the narrow cond ction angle demanded by capacitive inp t filters in switching power converters ca ses high harmonic content in the c rrent waveform, res lting in lower operating efficiency.

A viable sol tion to this problem is the incl sion of a power factor correction (PFC) stage to facilitate more efficient power sage as well as lowering the harmonic content of the line c rrent. The most pop lar topology for this task is the switched-mode boost converter. Here the boost converter stage is inserted between the inp t rectifier and the b lk storage capacitor. This forces the inp t c rrent to be in phase with the inp t voltage and provides a boosted D.C. voltage reservoir for the following power stage.

the other (SW1) t rns off. They are “ nsynchronized” when both are switched on at the same time.) Here SW1 and SW2 are switched on and off at the same time. The peak c rrents and therefore the ripple voltage are less than a PFC stage with a resistive load. Even f rther red ctions are possible by “synchronizing” the 2 stages (Fig res 4 and 5).

Micro Linear‘s ML4824 Combo Controller IC is an integrated sol tion for systems benefitting from the advantages made possible by synchronizing the 2 cascaded power stages. In this application note the differences between the traditional combo mod lation scheme ( nsynchronized or trailing edge mod lation) and the ML4824’s leading/trailing edge mod lation scheme are explained. A typical application is shown and test res lts are compared with the traditional approach. Then, a detailed look is taken inside the ML4824 and key design form las are reviewed which will enable sers to begin their own design.


In many instances the power s pply system m st interface to a wide range inp t voltage (80-264V) req iring the boosted voltage be eq al to or greater than 380VDC. For safe operation a capacitor with a voltage rating of at least 400V is necessary. Traditional cascaded power stages req ire large b lk capacitance val es with low ESR to minimize peak to peak ripple voltage and lower self heating. Together these req irements res lt in a costly capacitor.

The cascade connection of power stages is a very effective and powerf l tool in the design of state-of-the- art high freq ency switch mode power converters (1). In recent years, power factor corrected power converters are rapidly gaining pop larity. They offer improved performance when compared to traditional off-line switching power converters. However, special system stability considerations m st be made.

To nderstand why the b lk capacitor req irements are traditionally so stringent consider the circ it shown in Fig re 1, a PFC power stage with resistive load. The b lk capacitor C1 m st s pply load c rrent I0 when VSW is on, storing energy in the boost ind ctor L1. It m st also “absorb” the peak c rrent from L1 each time VSW switches off. The res lt of these c rrents into and o t of C1 is a large ripple voltage across it. It is this large c rrent with steep wavefronts that place the high demand on C1’s b lk capacitance and ESR val es to minimize o tp t ripple.

Next, consider Fig res 2 and 3, a PFC stage followed by an “ nsynchronized” PWM stage. (Note 1: In this note the terms “ nsynchronized” and “synchronized” are sed to describe the switching action of 2 power switches operating from the same system clock. The switches are “synchronized” when one of them (SW2) t rns on when

Traditional trailing edge mod lation res lts in a momentary no-load condition when the b ck switch is t rned off. This condition makes loop compensation diffic lt as it res lts in 2 poles located close to the RHPZ (Right Half Plane Zero) already in play beca se the boost ind ctor operates in contin o s cond ction c rrent mode. Synchrono s switching techniq es as employed in the ML4824 p sh these poles f rther o t in freq ency allowing nity gain crossover to be placed at as high as one-half the line freq ency.

For example, consider a single power stage boost converter as shown in Fig re 1. The load of this stage is connected to the o tp t filter and its val e affects the loop response of the converter. When the load is red ced, the poles d e to the ind ctor and the capacitor become closer and the phase margin is red ced.

REV. 1.0 11/17/2000

Document info
Document views45
Page views45
Page last viewedThu Jan 19 20:24:52 UTC 2017