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D.C. O.K. COMPARATOR, UNDER VOLTAGE, AND SOFT START

The D.C. O.K. comparator, U7 monitors the PFC o tp t to disable or enable the D.C. to D.C. PWM section. It also discharges the ISS pin. When the PFC o tp t reaches the design val e, the PWM section will monotonically ramp

p the D.C. o

tp

cost of the ho

se

13.0V V

CC

.

t voltage. This feat re will red ce keeping circ itry which generates

the a

The ISS will be p lled down d ring nder voltage locko t which will ens re a smooth transition to protect the components.

The PFC section also has the soft start feat re d e to the presence of the two transcond ctance amplifiers. Additional external soft start can be added, i.e., additional delay time can be config red to ca se a more grad al increase of the o tp t power, which is req ested by the PFC o tp t thro gh the Voltage Transcond ctance Amplifier.

VOLTAGE MODE WITH FEED-FORWARD RAMP

In the PWM section, a voltage mode control system can be config red instead of c rrent mode control, if desired. A feed-forward ramp can be realized by connecting a resistor between PFC high voltage D.C. o tp t and RAMP 2, and connecting a capacitor between RAMP 2 and GND.

REV. 1.0 11/17/2000

Application Note 34

CONCLUSION

An integrated sol tion which simplifies the off-line PFC power s pply design has been shown. Leading edge mod lation for synchrono s switching is the main feat re of this controller. Noise imm nity of the ML4824 is excellent beca se of the se of leading edge mod lation for the power factor correction stage and trailing edge mod lation for the D.C. to D.C. second stage. At the DC to DC stage, an internal discharge transistor on RAMP 2 red ces the switching noise right after the switch is on, so it does not req ire a leading edge blanking. Other feat res incl de c rrent-mode control, 16-pin package, soft start, on-chip sh nt reg lator, wide bandwidth error amplifier and many other fa lt detection f nctions. Finally, to achieve optimal off-line PFC/PWM cascade power converter design, we concl de:

  • 1.

    The synchrono s switching method sho ld be tilized;

  • 2.

    The d ty ratio of the second stage sho ld be close to 0.5.

For more information on a typical application, please see Application Note 33, “ML4824 Combo Controller Applications.”

REFERENCE

1.

Micro Linear ML4819 Data Sheet, Micro Linear Corporation, San Jose, California, 1993

  • 2.

    R.D. Middlebrook, “Topics in M ltiple-Loop Reg lators and C rrent-Mode Programming” IEEE Power Electronics Specialists Conference, 1985 Record, pp. 716-732.

  • 3.

    J. Dronik, “Is Cascade Connection of Power Converters Inefficient?” Proc. PCIM Power Conversion Conference pp. 34–43, 1993

  • 4.

    Micro Linear ML4821 Data Sheet, Micro Linear Corporation, San Jose, California, 1993

  • 5.

    Micro Linear ML4824 Data Sheet, Micro Linear Corporation, San Jose, California

6.

Micro Linear Application Note 33, Micro Linear Corporation, San Jose, California

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