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Application Note 34

In the cascade power stage, the load co ld be momentarily connected or disconnected. (See Fig re 2 for a boost-b ck cascade stage.) Many systems attempt to red ce the no load period by speeding p the loop response for the second stage and hence, a second ( s ally faster) clock has to be sed res lting in a more complicated system.

TRAILING EDGE MODULATION AND LEADING EDGE MODULATION

Conventional p lse width mod lation (PWM) employs trailing edge mod lation in which the switch will t rn on right after the trailing edge of the system clock. Then the error amplifier o tp t voltage is compared with the mod lating ramp. When the mod lating ramp reaches the level of the error amplifier o tp t voltage, the switch will be t rned OFF. When the switch is ON, the ind ctor c rrent will ramp p. The effective d ty cycle of the trailing edge mod lation is determined d ring the ON time of the switch. Fig re 3 shows a typical trailing edge control scheme.

In the case of leading edge mod lation, the switch is t rned OFF right at the leading edge of the system clock; when the mod lating ramp reaches the level of the error amplifier o tp t voltage, the switch will be t rned ON. The effective d ty-cycle of the leading edge mod lation is determined d ring the OFF time of the switch. Fig re 4 shows a leading edge control scheme.

L1 I1

D1

IO

VO

+

C1

VSW

VIN

GND

Figure 1. A Single Boost Power Stage with a Load.

2

THE OUTPUT VOLTAGE RIPPLE OF THE PFC STAGE

If the boost-b ck cascade power converter of Fig re 2 is applied to the off-line PFC/PWM power converter, the

  • o

    tp t ripple voltage of the PFC stage can be separated

into two portions. One portion is d e to the voltage drop across the C1‘s ESR. The other is d e to dv/dt of C1. Ass ming both converters are in the Contin o s Cond ction Mode (CCM), and conventional trailing edge mod lation witho t synchrono s switching is sed, the ripple voltage is

TotalRipple Voltage I2MAX

  • ESR

0.433 I2MAX C1 fPFC

(1)

I2MAX

Average Inp t Power Efficiency VINRMS

2

(2)

If the dv/dt ripple voltage is dominant, dv reaches maxim m when the phase of the inp t voltage waveform is at 60° or 120°.

One of the advantages of the new control scheme is that it req ires only one system clock. Switch 1 (SW1) t rns off and switch 2 (SW2) t rns on at the same instant to minimize the momentary no load period, th s lowering ripple voltage generated by the switching action. With synchrono s switching, the ripple voltage of the first stage is red ced. Fig re 5 shows the boost-b ck cascade power

I3

VO

L1

D1

I4

L2

I1

I2

SW2

+

SW1

C1

D2

C2

VIN

GND

Figure 2. A Cascade Boost-Buck Power Converter without Synchronous Switching.

REV. 1.0 11/17/2000

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