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Application Note 34

I3

VO

L1

D1

I4

L2

I1

I2

SW2

+

SW1

C1

D2

C2

VIN

GND

Figure 5. Synchronous Switching Cascade Power Converter.

converter with synchrono s switching which differs from Fig re 2 only in the switching seq ence. The ripple voltage of Fig re 5 is

APPLICATION CIRCUIT

POWER FACTOR SECTION

TotalRipple Voltage

  • I2MAX

  • I3

  • ESR

I M A X 2 0 4 3 3 C1 fPFC .

  • I3

(3)

SYNCHRONOUS SWITCHING IN OFF-LINE PFC-PWM CASCADE POWER CONVERTER

A 200W off-line PFC/PWM cascade converter has been eval ated. Fig re 6 shows the schematic of the 200W off-line PFC PWM cascade converter. The res lts show that the 120Hz component of the o tp t ripple voltage has been red ced by 30%.

The f nction of the power factor correction section is to ens re the c rrent follows the voltage in time and amplit de proportionally. This means that, for steady-state constant o tp t power conditions, the c rrent amplit de will follow the voltage amplit de in the same proportion at any instant in time. When the voltage amplit de is at 100%, c rrent amplit de will be maxim m. When the voltage is at 50% amplit de, the c rrent amplit de will be at half its maxim m val e.

The res lt is a sin soidal c rrent waveform in phase with the incoming sin soidal voltage waveform.

EXPERIMENTAL RESULTS

By virt e of the leading edge mod lation PFC stage, working together with the trailing edge mod lation PWM stage the system performance is enhanced. A comparison was made between the ML4824 and the ML4819 which employs trailing edge mod lation for both power stages. The ML4819 is designed to f nction as a peak c rrent controller with c rrent mode PWM for the o tp t stage. The test conditions are

C

DC

= 5 0 µ F , V

IN

= 2 2 0 V A . C . ,

The power factor correction section is comprised of a boost type power stage with primary side of ind ctor T1 as the inp t ind ctor. The secondary side is sed as an a xiliary voltage so rce for powering the control circ it.

Since this stage is concerned with c rrent processing, and the freq ency of the c rrent is related to the line freq ency, the voltage control loop for this section is forced to have a slow response to allow the c rrent to follow the voltage. This slow voltage loop response necessitates the addition of another power stage for faster and more acc rate voltage processing.

Average Inp t Power = 75W,

f

PFC

= 8 0 K H z , a n d L

PFC

= 1 . 5 m H

See Fig re 7.

The power factor correction section derives its timing from the same oscillator as the p lse width mod lation section. This section has its own c rrent limit comparator for c rrent mode control. A comparator is also sed for s pplying overvoltage protection commands.

4

REV. 1.0 11/17/2000

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