PULSE WIDTH MODULATOR SECTION FOR DC TO DC CONVERTER
lse width mod
lator section is config
red as a
controller for a two-switch forward converter. The switch c r r e n t i s s e n s e d v i a t h e v o l t a g e d r o p a c r o s s r e s i s t o r R 1 8 . R e s i s t o r R 1 9 a n d c a p a c i t o r C 1 7 f n c t i o n a s a n o i s e f The two switches toggle ON and OFF together at the same time. Reset of the primary side of the transformer T i l t e r .
i s f a c i l i t a t e d b y d i o d e s D 5 a n d voltage, high speed rectifiers. D
, which sho
ld be high
The oscillator freq ency is determined by the val es for R T a n d C T . T h e O N t i m e o f t h e o s c i l l a t o r i s g i v e n b y t following expressions: h e
R T C T 1n
1. 2 5
RT CT 0.51for VREF
Typically, for the example circ it, which is operating at
8 0 k H z , R T i s 5 2 . 3 k , a n d C T i s 4 7 0 p F .
Period, T TON TOFF 2TD
where TD represents the propagation delay (approximately 20ns) of the circ it.
PFC RAMP (RAMP 1)
The peak-to-peak amplit de of the PFC ramp is set by the two voltages derived from the 7.5V bandgap reference. Two comparators are sed. The pper threshold is 3.75V, the lower 1.25V. The potential difference between the two inp ts to these two comparators is 2.5 volts, which is the peak-to-peak amplit de of the ramp. This ramp is sed in the power factor correction section.
PWM RAMP (RAMP 2)
There is also a second ramp which can be derived from sensing the switch c rrent, or for voltage mode control, can be derived from the o tp t (feed-forward signal) of the power factor corrector. This second ramp is sed for control of the combo’s PWM DC-DC converter stage.
THE GAIN MODULATOR
The gain of the gain mod lator is a tomatically controlled by the voltage feedback amplifier o tp t voltage (VEAO) and the r.m.s. voltage (VRMS) from the rectifier inp t bridge. A third inp t to the gain mod lator is the 120Hz A.C. line inp t c rrent (IAC), which s pplies an in phase sin soidal reference.
REV. 1.0 11/17/2000
Application Note 34
To red ce noise, c rrent is sampled instead of voltage. A resistor at the IAC node connected to the line will generate an inp t c rrent to the gain mod lator.
The gain mod lator o tp t (I
) is also a 120Hz sine
wave. The q ality of this waveform is dependent entirely on the q ality of the line voltage. If the line voltage is noisy, the o tp t of the gain mod lator will also be noisy. This is the reason why the bandwidth of VRMS and VEAO
have to be low.
D.C. O.K. COMPARATOR
The o tp t voltage of the power factor correction section is monitored by the internal D.C. O.K. comparator. If the
tp t of this section is too low, the p lse width
mod lator section will not be permitted to t rn ON. Once the o tp t level reaches 380 volts DC, the p lse width mod lator section will commence switching, with a programmable soft-start interval.
The power factor correction section can also be config
to have soft start by two possible arrangements. (1) the
tp t of the c rrent error amplifier is high impedance,
and if the compensation network is tied to the reference
), then the power factor stage will soft start.
(2) If the first arrangement is not slow eno gh for safe starting, then extra components can be added to VEAO to
assist soft start.
VOLTAGE LOOP COMPENSATION AND WIDE BANDWIDTH TRANSCONDUCTANCE AMPLIFIER
The voltage loop compensation has been sped p with a high gain, wideband ncompensated transcond ctance stage. A niq e transcond ctance c rve is shown in Fig re 11 which is different from the conventional operational amplifier. The transcond ctance amplifiers on ML4824 exhibits low transcond ctance when the two inp ts of the amplifier are balanced; and transcond ctance will increase when the two inp t voltages are
nbalanced. Beca se of s ch enhancement while the system is slewing, the system bandwidth and the slew rate also increases.
The transcond ctance amplifier itself does not req ire local feedback compensation. Loop compensation is also m ch easier to manage.
To design a compensation network, it is req ired to find the power stage voltage transfer f nction. However, a precise PFC stage model is not available at high freq encies.
The conventional approach is to obtain a first order approximation. Below 30Hz or at half of the line freq ency, the c rrent mode model described in (2) is valid since the PFC stage never reaches the steady state above 30Hz.