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Application Note 34

The PFC stage is a resistor em lated at the line freq ency. At the line freq ency, the instantaneo s inp t power, which is A.C., is not eq al to the instantaneo s o tp t power, which is D.C. The instantaneo s inp t power at the peak of the voltage waveform delivers more power than the average power req ired. Therefore the excessive power m st be stored temporarily in the high voltage reservoir capacitor. At freq encies above the line freq ency the instantaneo s system power has not reached the steady state. Therefore the D.C. operating point for A.C. analysis cannot be determined. However below one half of the line freq ency, the system operating point can be averaged based on the average inp t power.

For the voltage loop response above the line freq ency, the first order model is simply a c rrent so rce feeding the high voltage capacitor. See Fig re 9.

VOUT V E A O

AVERAGE P N

V V O U T D C E A O

  • S CDC

VOUT DC AVERAGE P N 5.3V S CDC

(7)

Here the swing of the voltage loop error amplifier is 5.3V. This transfer f nction indicates the zero crossing f r e q e n c y , W C w h i c h i s

VOUT DC Average PIN 5.3 S CDC

(8)

At freq encies below one half of the line freq ency, the conventional c rrent mode model can be applied.

VOUT VEAO

W

P

V

O

W

C

+

V

P OUTDC

IN dV

EAO

C

DC

AAMP(S)

S

=

S

Figure 9. High Frequency Power Stage Model for Voltage Loop.

Figure 10. Overall Voltage Loop Response.

250

250

200

200

Transconductance (µ )

150

100

Transconductance (µ )

150

100

50

50

0

0

1

2

V

FB

(V)

3

4

5

0

  • 500

0 IEA Input Voltage (mV)

500

Figure 11. Voltage Loop OTA, U1, and Current Loop OTA, U2, Transconductance, GM.

8

REV. 1.0 11/17/2000

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