The model depicts a pole location. When the d ty cycle is 1, the pole is
(9) RL CDC
Now the compensation network can be designed. If lead lag compensation is applied, the loop crossover freq ency can be set aro nd 30Hz ass ming 60Hz line freq ency. See Fig re 10.
CURRENT LOOP COMPENSATION WITH WIDE BANDWIDTH TRANSCONDUCTANCE AMPLIFIER
The c rrent loop error amplifier is a high performance, wideband ncompensated transcond ctance amplifier. The designer can adj st his own bandwidth based on the system req irement. See Fig re 11.
A proced re similar to the voltage loop can be sed to obtain the transfer f nction for the power stage of the c rrent loop. At high freq encies, the power stage behaves as a voltage so rce driving an ind ctor. See Fig re 12.
RSENSE R C P P V T T VIN L
RSENSE VIN 2.5V L
2 RL CDC
VR C P P TT -
Figure 12. High Frequency Power Stage Model for Current Loop.
REV. 1.0 11/17/2000
Application Note 34
CURRENT GAIN MODULATOR AND MAXIMUM AVERAGE POWER LIMIT
The f nction of the c rrent gain mod lator is similar to the method sed in ML4821 to generate a reference sine wave c rrent in phase with the line voltage. The maxim m inp t power is also set by the gain mod lator.
The gain K is c rve fitted to 1/V
gain to simplify
niversal inp t design mod lators (see Fig re 13). Below 1.2V, K enters a brown o t protection region and will not
fit the 1/V
c rve. This feat re can be sed to set the
minim m A.C. inp t voltage s ally 80VAC. The , maxim m c rrent is limited at 200µA internally. is an on-chip resistor of 3.5K. The high loop I R GM(OUT) GM(OUT)
gain and the high bandwidth c rrent loop amplifier will
(3.5K) eq al to keep the prod ct of I xR GM(OUT) GM(OUT) GM(OUT) is eq al to K x (V x I I N . S i n c – 1.5) x R SENSE AC e I AC GM(OUT) EAO , and I is derived from the rectified sin soidal line I is a sine wave reference generated in voltage, I
phase with the sin soidal line voltage.
TIMING DIAGRAM AND HOW TO IMPLEMENT DOUBLE FREQUENCY PWM FOR ML4824-2
There are two versions of the ML4824 available. In the ML4824-1, the PFC switching freq ency is eq al to the PWM switching freq ency. These two sections synchronize at the rising edge of the system clock. In the ML4824-2, the PWM switching freq ency is eq al to twice the PFC switching freq ency.
To implement f
t h e R T C T r a m p h a v e b e e n
sed as a reference ramp and 4 timing areas have been generated. See Fig re 14.
Variable Gain Block Constant - K
Figure 13. Gain Modulator Gain, (K).