12) The FPGA device must be programmed and conﬁgured to implement the designed circuit. The required conﬁguration ﬁle is generated by the Quartus II Compiler’s Assembler module. Altera’s DE2 board allows the conﬁguration to be done in two different ways, known as JTAG and AS modes. The conﬁguration data is transferred from the host computer to the board by means of a cable that connects a USB port on the host computer to the leftmost USB connector on the board. In the JTAG mode, the conﬁguration data is loaded directly into the FPGA device. The acronym JTAG stands for Joint Test Action Group. If the FPGA is conﬁgured in this manner, it will retain its conﬁguration as long as the power remains turned on. The conﬁguration information is lost when the power is turned off. The second possibility is to use the Active Serial (AS) mode. In this case, a conﬁguration device that includes some ﬂash memory is used to store the conﬁguration data. Quartus II software places the conﬁguration data into the conﬁguration device on the DE2 board. Then, this data is loaded into the FPGA upon power-up or reconﬁguration. Thus, the FPGA need not be conﬁgured by the Quartus II software if the power is turned off and on.
13) We will be using Active Serial mode of configuration. In this case, the conﬁguration data has to be loaded into the conﬁguration device on the DE2 board, which is identiﬁed by the name EPCS16. To specify the required conﬁguration device select Assignments >Device, which leads to the window in Figure 21. Click on the Device & Pin Options button as shown in Fig. 22 to reach the window in Figure 23. Now, click on the Conﬁguration tab. In the Conﬁguration device box (which may be set to Auto) choose EPCS16 and click OK. Upon returning to the window in Figure 22, click OK. Recompile the designed circuit.