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Fig. 20

12) The FPGA device must be programmed and configured to implement the designed circuit. The required configura­tion file is generated by the Quartus II Compiler’s Assembler module. Altera’s DE2 board allows the configuration to be done in two different ways, known as JTAG and AS modes. The configuration data is transferred from the host computer to the board by means of a cable that connects a USB port on the host computer to the leftmost USB connector on the board. In the JTAG mode, the configuration data is loaded directly into the FPGA device. The acronym JTAG stands for Joint Test Action Group. If the FPGA is configured in this manner, it will retain its configuration as long as the power remains turned on. The configuration information is lost when the power is turned off. The second possibility is to use the Active Serial (AS) mode. In this case, a configuration device that includes some flash memory is used to store the configuration data. Quartus II software places the configuration data into the configuration device on the DE2 board. Then, this data is loaded into the FPGA upon power-up or reconfiguration. Thus, the FPGA need not be configured by the Quartus II software if the power is turned off and on.

13) We will be using Active Serial mode of configuration. In this case, the configuration data has to be loaded into the configuration device on the DE2 board, which is identified by the name EPCS16. To specify the required configuration device select Assignments >Device, which leads to the window in Figure 21. Click on the Device & Pin Options button as shown in Fig. 22 to reach the window in Figure 23. Now, click on the Configuration tab. In the Configuration device box (which may be set to Auto) choose EPCS16 and click OK. Upon returning to the window in Figure 22, click OK. Recompile the designed circuit.

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