7) We can specify any third-party tools that should be used for the project. For this project we need to choose the Modelsim(VHDL) tool under the EDA Simulation Tool option. After Selecting this tool press Next.
8) A summary of the chosen settings appears in the screen shown in Figure 9. Press Finish, which returns to the main Quartus II window, but with the new project specified in the display title bar.
9) The VHDL code in the ﬁle is processed by several Quartus II tools that analyze the code, synthesize the circuit, and generate an implementation of it for the target chip. These tools are controlled by the application program called the Compiler. Run the Compiler by selecting Processing >Start Compilation, or by clicking on the toolbar icon that looks like a purple triangle as shown in Figure 10. As the compilation moves through various stages, its progress is reported in a window on the left side of the Quartus II display as shown in Figure 11. Successful (or unsuccessful) compilation is indicated in a pop-up box. Acknowledge it by clicking OK, which leads to the Quartus II display as shown in Figure 12. In the message window, at the bottom of the ﬁgure, various messages are displayed. In case of errors, there will be appropriate messages given. When the compilation is ﬁnished, a compilation report is produced. This window can be opened at any time either by selecting Processing >Compilation Report or by clicking on the icon. The report includes a number of sections listed on the left side of its window.