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Fig. 12

10) Quartus II software displays messages produced during compilation in the Messages window. If the VHDL design file is correct, one of the messages will state that the compilation was successful and that there are no errors. If the Compiler does not report zero errors, then in that case a message corresponding to each error found will be displayed in the Messages window. Double-clicking on an error message will highlight the offending statement in the VHDL code in the Text Editor window. Similarly, the Compiler may display some warning messages. Their details can be explored in the same way as in the case of error messages. Correct the errors if any and recompile the design.

11) After Compilation is done, Simulation needs to be done to verify the correctness of the design. To run the simulation go to Assignments Menu and click Settings. In the window that pops up, under the Simulator Settings, set the Simulation Mode to Functional as shown in Figure 13. If you want to use the .do file for your simulations you can specify the file under the EDA Tool Settings->Simulation as shown in Figure 14. After these settings are done go to Tools Menu and run the EDA Simulation Tool ->EDA RTL Simulation, this will pop up the Modelsim window in which the simulation can be performed. If you are using .do file to run your simulation you need to specify the working directory where your design is compiled as shown in Figure 15.

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