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ISSCC 2011 TRENDS REPORT - page 10 / 16

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10 / 16

100

10

x 3 / year

1

    • 4bit/cell (16LC)

    • 3bit/cell (TLC)

      • 0.1

        2bit/cell (MLC)

        • 1bit/cell (SLC)

0.01

1994 1996 1998 2000 2002 2004 2006 2008 2010 2012 Year

Figure 7 NAND Flash Memory Trends

SRAM BITCELL DESIGN

Historically, a 50% area reduction in bitcell from node to node has been enabled by the scaling of technology feature size, resulting in a 2x improvement in on-die memory integration with each node reduction and continuing improvements in performance. However, the reduction in transistor geometry is increasing device variability, resulting in a slowdown in the scaling trend as shown in Figure 8. Between the 45nm and 32nm technology nodes, bitcell scaling has been reduced to less than the typical 50%. The introduction of High-κ Metal Gate technologies at the 45nm node has provided a significant reduction in the equivalent oxide thickness, thereby reducing the VT mismatch and allowing further aggressive scaling of device dimensions needed to achieve the scaling of area. However, technology improvements alone are not sufficient to maintain area scaling. SRAM peripheral-circuit-assist features have become the key to maintaining cell stability, readability and write margins, and enable low-voltage operation. New strategies ranging from circuit-level techniques to fundamental changes in array architecture can also enable significant gains in area and power efficiency.

Memory density [MB/mm ]

2

©Copyright 2011 ISSCC

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