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ISSCC 2011 TRENDS REPORT - page 11 / 16

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SRAM Bitcell Area and VDD Trends

4.0 2.0

50% Area Scaling

30-40% Scaling

1.5

2

Bitcell Area (μm )

1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1

Thin Bitcell Introduction

High-K MG Introduction

?

1.2 1.1 1.0

0.9 0.8

VDD (V)

180

130

90 65 45 32 Technology Node (nm)

22

14

2011 ISSCC Tutorial

1

Figure 8 SRAM Bitcell Trends

DRAM & HIGH-SPEED I/O

Unfortunately, the gap between memory-core frequency and external-data rate continues to increase as conventional high-speed wired interface schemes such as DDRx and GDDRx for DRAM and NAND flash memory continue to evolve (Figure 9). This leads to the need for a larger prefetch size, which is emerging as a major problem in modern memory systems. However, alternatives which accommodate high data rates through the use of wider or differential interfaces will face the problem of increased pin-counts, and enlarged silicon areas. Combined with 3D integration of memory and memory/logic in near-future commercial products, new interface technologies will yield more memory stacking, along with lower-power and higher- bandwidth interfaces.

©Copyright 2011 ISSCC

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