X hits on this document

PDF document

ISSCC 2011 TRENDS REPORT - page 2 / 16





2 / 16

performance that matches, and now even exceeds, what was possible in traditional high- performance analog IC technology.


While process technology continues its onward advancement, enabling integration on massive scales, this year’s processors come from wide technological backgrounds. New ground is broken in key areas of transistor integration, performance per unit power, and functional integration. This is accomplished across a wide range of process technologies – 65nm, 45nm, 40nm, and 32nm bulk and SOI CMOS technologies.

The chip-complexity chart (Figure 1) shows the trend in integrating transistors on a single chip over the past two decades. While the 1 billion limit was passed some 5 years ago, this year marks the first commercial product exceeding 3 billion transistors on a single die with the 32nm Intel Itanium Processor. The massive integration continues to drive the inclusion of large caches on-die as we see with 30MB on IBM’s zEnterprise, and 54MB on the 32nm Intel Itanium.

Aggressive processor power management and system-wide power optimization has become a requirement as technology has enabled the increasing trend of system integration onto the processor die (Figure 2). The trend of flat-to-down power in these systems continues as engineers leverage low-power design features to squeeze performance within existing power budgets. For example, the IBM zEnterprise system achieves a 20% frequency boost to a mind- numbing 5.2GHz with no power envelope increase over prior generation devices (Figure 3). The Godson-3B processor’s focus on power enables that device to consume only 40W. The increased focus on power is helping rein in the immense demands, which PCs, servers, data centers, and similar systems put on power grids. The result will be lower cost, less cooling demands, and a greener product.

As a consequence of lower-power design requirements, system architects have been forced to innovate using multiple processor cores typically running parallel threads at lower frequencies (Figure 4). This enables processors to turn off when not actively doing computations. While ISSCC 2011 does not break ground in maximum core count, the body of work continues to emphasize this growing trend – IBM’s zEnterprise is a 4-core machine, the Intel Westmere-EX delivers a 10-core solution, China’s Godson-3B features 8 cores, and AMD’s Bulldozer also delivers an 8-core CPU. This flexibility and scalability will enable adaptable system power profiles, further reducing power consumption and improving the end-user experience, as our multi-tasking lifestyle evolves.

These trends in integration, power consumption, and parallel computation, bring new challenges to processor development: New techniques are required to ensure robustness to power supply fluctuations; and improvements in power/clock delivery networks are required as multiple voltage domains become de facto on these chips. ISSCC 2011 will highlight many of these new building-block technologies.

©Copyright 2011 ISSCC

Document info
Document views19
Page views19
Page last viewedSat Oct 22 22:23:10 UTC 2016