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Four-Resistor Bias Network for BJT (cont.)

  • All calculated currents > 0,

    • 4.32

      = - 3.62 V

=

-

= 0.7 -

H e n c e , b a s e - c o l l e c t o r j u n c t i o n i s r e v e r s e - b i a s e d , a n d a s s u m p t i o n o f f o r w a r d - a c t i v e r e g i o n o p e r a t i o n = + α = 1 2 3 8 , 2 0 0

The two points needed to plot the load L o a d - l i n e f o r t h e c i r c u l i n e a r is correct. e ( 0 , 1 2 V ) a n d ( 3 1 4 μ A , 0 ) . R e s u l t i n g l o a d l i n e i s p l o t t e d o n common-emitter output characteristics.

= 2.7 μA, intersection of corresponding characteristic with load line gives Q-point.

33

Four-Resistor Bias Network for BJT: Design Objectives

We know that

=

for

<< (

)

This implies that

<<

so that

=

. So base current doesn’t disturb

voltage divider action. Thus, Q-point is independent of base current as

well as current gain.

Also,

is designed to be large enough that small variations in the

assumed value of

won’t affect

.

Current in base voltage divider network is limited by choosing I2 IC/5.

This ensures that power dissipation in bias resistors is < 17 % of total

quiescent power consumed by circuit and

>>

for β > 50.

34

17

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