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AVR32709: AVR32 UC3 Audio Decoder Over USB - page 21 / 29

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AVR32709

6.4.6

FAT File System The FAT12/16/32 files is located in the directory /SERVICES/FAT/.

6.4.7

Board Definition Files The application is designed to run on Atmel Evaluation Kits. All projects are configured with the following define: BOARD=EVKxxxx. The EVKxxxx definition can be found in the /BOARDS/EVKxxxx directory.

6.4.7.1

Board customization

IAR’ project, open the project options (Project -> Options), choose the «C/C++ Compiler», then «Preprocessor». Modify the ‘BOARD=EVKxxxx’ definition by ‘BOARD=USER_BOARD’.

GCC’, just modify in the ‘config.mk’ file (/APPLICATIONS/AUDIO-PLAYER/<part>- <board>-<feature(s)>/GCC/) the DEFS definition with ‘-D BOARD=USER_BOARD’.

AVR32 Studio’, open the project properties (Project -> Properties), go in the «C/C++ build», then «Settings», «tool settings» and «Symbols». Modify the ‘BOARD=EVKxxxx’ definition by ‘BOARD=USER_BOARD’.

The HMI can be easily changed. See Section 6.4.4 “HMI Communication Task Example” on page 19 for more details.

6.4.8

Audio Rendering Interface The audio DAC mixer source code is lodated in /SERVICES/AUDIO/AUDIO_MIXER/audio_mixer.c,h.

6.4.8.1

I2S using SSC module The /COMPONENTS/AUDIO/CODEC/TLV320AIC23B/ directory contains the driver for the external DAC TLV320AIC23B.

The UC3 communicates with the TLV320AIC23B with the Two Wire Interface (TWI). The UC3 is the TWI master.

The AVR32 SSC module generates I2S frames using internal DMA (PDCA) to free CPU cycles for audio decoding.

Each time a new song is played, the SSC module is configured corresponding to the sample rate of the new song. The SSC clocks are composed of a bit clock and a frame sync:

t from the audio stream. For a 44.1 KHz sample rate, the bit clock will be 44100 x 2 (stereo) x 16 (bits per channel) i.e. 1.411 MHz.

example.

To get accurate 44.1KHz audio frequency samples, an external 11.2896 MHz oscillator is used as input to an internal PLL and source the CPU/HSB/PBA/PBB frequency with 62.0928 MHz.

The TLV320AIC23B uses a master clock (MCLK) of 11.2896 MHz, outputed by the UC3 through a generic clock. Then, the generic clock output (PA07) is connected to the MCLK of the TLV320AIC23B.

The SSC clock divider in CMR register is given by:

SSC.CMR.DIV = Round (FPBA / (2 x(FSampleRateSetPoint

x NumberChannel x BitsPerSamples))

21

7817D–AVR32–05/11

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