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AVR32709: AVR32 UC3 Audio Decoder Over USB - page 22 / 29

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6.4.8.2

22

set point (Hz)

Actual Sample Rate (Hz)

Relative Error (%)

(semitones)

8000

8018

0.23

0.04

11025

11025

0.00

0.00

16000

15095

-0.59

-0.10

22050

22050

0.00

0.00

32000

32340

1.06

0.18

44100

44100

0.00

0.00

48000

48510

1.06

0.18

The real frequency sample rate output by the SSC is given by:

= FPBA / (2 x SSC.CMR.DIV x NumberChannel x BitsPerSamples) Note: NumberChannel = 2, BitsPerSamples = 16, FPBA = 62.0928 MHz FActualSampleRate Note:

The music interval in semitones is:

MusicInterval (semitones) = LOG( ( FActualSampleRate

/ FSampleRateSetPoint

) / (2

1/12

))

Music Interval

Table 6-1.

Sample rate

Samples rate with SSC module

For further information, please refer to the “AVR32788: AVR®32 How to use the SSC in I2S mode” application note.

ABDAC

The ABDAC driver is located in /DRIVERS/ABDAC.

The

e x t e rna l

a m pl i f i er

d ri v e r

(TPA6130A)

is

located

in

/COMPONENTS/AUDIO/AMP/TPA6130A.

The AVR32 ABDAC module is using the internal DMA (PDCA) to free CPU cycles for audio decoding.

To get accurate audio frequency samples, the two external oscillators 12 MHz (OSC1) and 11.2896 MHz (OSC0) are used to source (directly or through a PLL) the ABDAC generic clock.

Sample rate set point (Hz)

ABDAC Generic clock input frequency

Actual Sample Rate (Hz)

Relative Error (%) 1.06 0.00 -2.34 0.00

Music Interval (semitones)

8000 11025 16000 22050

PLL0 OSC1 PLL1 OSC1

8085 11025 15625 22050

0.18 0.00 -0.41 0.00

The PLL0 output frequency is 62.0928 MHz. The PLL1 output frequency is 48 MHz (used for

Refer to /DRIVERS/ABDAC/abdac.c for the configuration of the ABDAC generic clock.

Table 6-2.

Samples rate with ABDAC module

USB). When used, the ABDAC generic clock divider is given by: ABDAC generic clock divider = Round (FGCLKInput / (2 x 256 x (FSampleRateSetPoint

)) -1)

AVR32709

7817D–AVR32–05/11

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