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PIC12F683 Rev. A Silicon/Data Sheet Errata - page 2 / 6

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PIC12F683

FIGURE 8-2:

COMPARATOR C1 OUTPUT BLOCK DIAGRAM

PORT Pins

MULTIPLEX

C1

CINV

To COUT

Rev. B1: To ECCP Auto-Shutdown

To Data Bus

D

Q

Q1

EN

RD CMCON0

Set CMIF bit

D

Q

Q3*RD CMCON0

EN CL

Rev. A1: To ECCP Auto-Shutdown

Reset

Note 1: 2:

Q1 and Q3 are phases of the four-phase system clock (FOSC). Q1 is held high during Sleep mode.

FIGURE 1:

SILICON REVISION A1 VS. REVISION B1

A1 CCP Output

B1 CCP Output

COUT

CMIF

Uncertainty due to Q1 cycle delay

Read CMCON0

Uncertainty due to Q1 cycle delay

Read CMCON0

DS80196F-page 2

© 2007 Microchip Technology Inc.

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