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41

this would happen at the bit level, however this lets the jamming have a greater effect on the

system. Figure 17 shows how the decisions placed on the chip can improve the worst-case

jamming of the SESS system with iterative detector when the noise of the channel is negligible.

BER vs. Eb/No N=32 Tx=100,000

BER

10-1

10-2

10-3

jdc = 0.75 jdc = 0.80 jdc = 0.85 jdc = 0.90 jdc = 0.95 jdc = 1 AWGN

10-4

10-5

10-6

  • 0

    2

4

6

8

10

Eb/Nj (dB)

Figure 17 - Worst-Case Jamming SESS Chip Decision

It should be noted that the chip decision improves the worst-case jamming, and that the

worst-case is when the jamming duty cycle is 100 percent (every bit is jammed or ρ =1). As the

jamming duty cycle gets lower, the BER gets better, proving that it works. In fact, it improves

the worst-case jamming by 6 db at a BER of 10-3 over the bit decision, which is 12 db over

DSSS.

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