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The success of the chip decision in the worst-case scenario can be attributed to the way it

handles jamming at low ρ values. At the lower ρ values, chips have a lower chance of being

jammed. When the decision is made at the chip level it weighs out effects of higher power

jamming, as the jammed chip only attributes 1/N of the final hard decision (1/2N with iterative

detector). Thus, at the lowest level of ρ, the majority of the data being sent is not jammed and

sent through a noiseless channel. The noiseless channel makes it easy for the chip decision

detector to recover from errors at lower ρ. This being the case, the jamming over the channel no

longer dominates the noise of the channel. This reveals the need to add noise or fading back to

the channel during the jamming simulations.

7.3 Results

There remain problems with the chip decision approach in the assumptions made of the

simulations used thus far in the paper. The first problem is that the chip decision is actually

lower performance under the standard AWGN channel and in a Rayleigh fading channel (can be

seen in Figure 16 on the next page)

With ρ equal to one, chip decision is about 2.5 db worse than in the bit decision on both

the AWGN and Rayleigh fading channels. Figure 17 shows that under jamming the chip

decision does better, but Figure 17 shows in noise channels without jamming bit decision is

better. This brings rise to the second problem; when jamming the assumption is that the noise of

the channel is negligible.

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