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Microsoft Windows Logo Program System and Device Requirements  —  145

B10.2.4.2 DELETED
B10.2.4.3 DELETED
B10.2.4.4 ATA controllers and devices support Ultra DMA, do not claim 3F7h and 377h

The programming register set for PCI Integrated Device Electronics (IDE) bus master DMA is defined in ATA/ATAPI-5 (or later). ATA drives must comply with ATA-5 to ensure fully featured hardware and Windows-compatible device driver support.

All controllers and ATA hard drive peripherals must support Ultra DMA at transfer rates of 33 MB per second or higher as defined in ATA/ATAPI-5 (or later). In addition to improved transfer rates, Ultra DMA also provides error checking for improved robustness over previous ATA implementations. ATA controllers incorporated into PCI chip sets must implement DMA.

Definitions for the ACPI control methods can be found in Section 10.8 of ACPI 1.0b.

See A3.4.5.

B10.2.4.5 Dual ATA adapters use single FIFO with asynchronous access or dual FIFOs and channels; ATA disk drive supports

If implemented, dual ATA adapters use single FIFO with asynchronous access or dual FIFOs and channels

Although the use of an ATA adapter with more than one channel is optional, if included, dual ATA adapters must be designed so that either channel might be used at any time; the operating system does not have to serialize access between the primary and secondary channel. This requirement means either that the two channels are totally independent or that anything shared. For example, a programmed I/O (PIO) read prefetch buffer is protected by a hardware arbitrator.

Section 5.0 of the BIOS Boot Specification, Version 1.01 defines an implementation for dual asynchronous channels.

A design implementing a single first in/first out (FIFO) that uses a hardware solution to synchronize access to both channels meets this requirement. A request on one channel need not be completed before another request to the other channel can start. A software-based solution is not acceptable.

See A1.1.4.11.

ATA-based systems must be tested with ATA DMA enabled; the system must not have an embedded single-FIFO dual-channel ATA controller.

*EFI Note: Section 5.0 of the CIP BIOS Boot 1.01 defines the implementation for dual asynchronous channels. Note that this particular issue is also relevant for EFI systems, and designers of these systems will also use this specification for clarification of this particular implementation issue even though the rest of this specification is superseded by EFI.

Dual-channel controllers that require special software to serialize channel I/O for a single prefetch FIFO do not meet these requirements. Such designs require serial access to one of four devices, defeating the primary advantage of asynchronous dual-channel controllers. Furthermore, such devices are non-standard and require custom driver support.

B10.2.4.6 Controller and peripheral connections include Pin 1 cable designation with keyed and shrouded connectors

One edge of the keyed ribbon cable and the keyed connector of the ATA or ATAPI controller and peripheral device must indicate the Pin 1 cable orientation. Designation of the keyed connector must be clearly indicated on or near the connector.

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