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Microsoft Windows Logo Program System and Device Requirements  —  147

B10.3.2 SCSI Controllers/Devices - Industry Standards

Note: This list provides complete titles and web locations for references cited. The listing of a reference here does not imply that complete compliance with that reference is a Windows Logo Program requirement.  

B10.3.2.1 Small Computer Interface (SCSI-3) standard

Global Engineering Documents at http://global.ihs.com/.

B10.3.2.2 SCSI Parallel Interface (SPI-4) standard or later

B10.3.3 SCSI Controllers/Devices - Quality

B10.3.3.1 Passes WHQL tests - See B1.3, B10.1.4.7.

See “SCSI Controllers” and device-specific topics in HCT documentation.

B10.3.4 SCSI Controllers/Devices - Windows Experience

B10.3.4.1 DELETED
B10.3.4.2 DELETED
B10.3.4.3 Large partition support (>8 GB) and ability to boot from loader is supported
B10.3.4.4 Adapter is capable of sharing IRQ and works behind a PCI-PCI bridge

System designers must make a best effort to provide access to non-shared interrupt lines by meeting these conditions:

The system design enables all PCI slots and PCI device types to obtain exclusive use of an interrupt line when exclusive access increases performance.

Dedicated PCI interrupts must not use vectors from ISA bus interrupts.

The high-end and low-end commodity server platforms present certain design challenges. For high-end servers, PCI 2.2 taken by itself imposes a limitation for Intel Architecture-based systems because the values written to the Interrupt Line register in configuration space must correspond to IRQ numbers 0-15 of the standard dual 8259 configuration, or to the value 255 which means “unknown” or “no connection.” The values between 15 and 255 are reserved. This fixed connection legacy dual 8259 configuration, if examined alone, constrains Intel Architecture-based systems, even when they use sophisticated interrupt-routing hardware and APIC support. For low-end servers, some core logic offerings provide little or no interrupt-routing support, and designers implement rotating access to interrupt resources using simple wire-OR techniques, such as those illustrated in the implementation note in Section 2.2.6 of PCI 2.2.

Windows, with its support for both MPS 1.4 and ACPI on 32-bit platforms and ACPI on Itanium systems, uses mechanisms beyond the legacy methods of routing all PCI interrupts through the legacy cascaded 8259 interrupt controllers to determine proper allocation and routing of PCI bus IRQs. This Windows capability allows use of interrupts beyond the 0-15 range permitted by the strict reading of the current PCI 2.2 specification language for Intel Architecture systems. System designers should include sufficient interrupt resources in their systems to provide at least one dedicated interrupt per PCI function for embedded devices and one interrupt per PCI INTA# - INTD# line on a PCI slot. This will become a requirement for all servers in a future version of this guideline.

When system designers cannot provide a non-shared interrupt line to a particular PCI device or slot because of the situations cited, the server system’s documentation must explain clearly to the end

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