X hits on this document

425 views

0 shares

0 downloads

0 comments

72 / 174

Microsoft Windows Logo Program System and Device Requirements  —  72

B2.5.1 PCI Controllers/Devices - Windows Compatibility

B2.5.1.1 Driver device class support in related DDKs

Bus driver support is built in to Windows; see device class-specific entries in the Windows DDK.

B2.5.1.2 Windows compatibility and implementation notes (general)

http://www.microsoft.com/hwdev/bus/pci/

Note: This is a general reference, not a requirement.

B2.5.1.3 PCI Device Subsystem IDs and Windows

http://www.microsoft.com/hwdev/bus/pci/pciids.asp

See B2.5.3.2.1

B2.5.1.4 Compatibility Testing for Hot-Plugging Support for PCI Devices

http://www.microsoft.com/hwdev/bus/pci/hotplugpci.asp

Note: This is a general reference, not a requirement.

B2.5.1.5 DELETED
B2.5.1.6 See A1.1.5.3
B2.5.1.7 Correct PCI implementations

If PCI is present in the system, the PCI bus and PCI expansion connectors must meet the requirements defined in the PCI 2.2 specification, plus any additional PCI requirements listed here.

B2.5.3.2.1 Device IDs include PCI Subsystem IDs.

The Subsystem ID (SID) and SVID fields must comply with the SID requirement in PCI 2.2 and the implementation details provided in “PCI Device Subsystem IDs and Windows” at http://www.microsoft.com/hwdev/bus/pci/pciidspec.asp.

AMR devices and MR devices on the system board are not exempt from the requirement for SID and SVID.

See also A1.1.3

B2.5.3.2.2 System does not contain ghost devices.

Bus designs must fully implement all bus requirements on every expansion card connector. A computer must not include any ghost devices, which are devices that do not correctly decode the Type 1/Type 0 indicator. Such a device will appear on multiple PCI buses. A PCI card should be visible through hardware configuration access at only one bus/device/function coordinate.

B2.5.3.2.3 System uses standard method to close base address register (BAR) windows on nonsubtractive decode PCI bridges.

Nonsubtractive decode PCI bridges must implement the standard method to close BAR windows as defined in the PCI to PCI Bridge Architecture Specification Rev. 1.1. Setting the BAR to its maximum value and the limit register to zeros effectively closes the I/O or memory window references in that bridge BAR.

B2.5.3.2.4 See B10.1.4.6

© 1999-2002 Microsoft Corporation. All rights reserved.

Document info
Document views425
Page views425
Page last viewedTue Dec 06 08:24:53 UTC 2016
Pages174
Paragraphs4629
Words57695

Comments