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Microsoft Windows Logo Program System and Device Requirements  —  73

B2.5.3.2.5 DELETED
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B2.5.3.2.7 Configuration Space is correctly populated.

PCI 2.2 describes the configuration space used by the system to identify and configure each device attached to the bus. The configuration space is made up of a header region and a device-dependent region. Each configuration space must have a 64-byte header at offset 0. All the device registers that the device circuit uses for initialization, configuration, and catastrophic error handling must fit within the space between byte 64 and byte 255.

All other registers that the device uses during normal operation must be located in normal I/O or memory space. Unimplemented registers or reads to reserved registers must complete normally and return zero. Writes to reserved registers must complete normally, and the data must be discarded.

All registers required by the device at interrupt time must be in I/O or memory space.

B2.5.3.2.8 Interrupt routing is supported using ACPI.

The system must provide interrupt routing information using a _PRT object, as defined in Section 6.2.3 of ACPI 1.0b (for x86-based systems) and Section 6.2.8 of ACPI 2.0 (for Itanium-based systems). It is important to note that the _PRT object is the only method available for interrupt routing on Itanium-based systems.

B2.5.3.2.9 DELETED
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B2.5.3.2.11 DELETED
B2.5.3.2.12 PCI devices decode only resources found in the Devices BAR.

PCI devices must not decode cycles that are not their own to avoid contention on the PCI bus. Notice that this requirement does not in any way prohibit the standard interfaces provided for by the PCI cache support option discussed in PCI 2.2, which allows the use of a snooping cache coherency mechanism. Auxiliary hardware that is used to provide non-local console support is permitted within the scope of this requirement.

B2.5.2 PCI Controllers/Devices - Industry Standards

Note: This list provides complete titles and web locations for references cited. The listing of a reference here does not imply that complete compliance with that reference is a Windows Logo Program requirement.  

B2.5.2.1 PCI Bus Power Management Interface Specification, Revision 1.1 or later
B2.5.2.2 PCI Bus Power Management Interface Specification for PCI-to-CardBus Bridges

Details are cited in PCCard-19 of PC Card and CardBus Guidelines, Version 1.1.

B2.5.2.3 PCI Local Bus Specification, Revision 2.2 (PCI 2.2) or later
B2.5.2.4 PCI to PCI Bridge Architecture, Revision 1.1

http://www.pcisig.com/specifications/pci_to_pci_bridge_architecture

© 1999-2002 Microsoft Corporation. All rights reserved.

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