Microsoft Windows Logo Program System and Device Requirements — 74
B220.127.116.11 PCI-X Specification, Revision 1.0
B18.104.22.168 Mini PCI Specification, Revision 1.0
B22.214.171.124 PCI Hot-Plug Specification, Revision 1.0
B2.5.3 PCI Controllers/Devices - Quality
WHQL Test Specification References: Chapter 4: PCI Test Specification
B126.96.36.199 Pass WHQL tests - See B1.3
Search for “PCI” to identify system-specific and device-specific topics in the HCT documentation.
B188.8.131.52 - See B184.108.40.206
B2.5.4 PCI Controllers/Devices - Windows Experience
B220.127.116.11 Power management supported as defined in PCI Bus Power Management Interface Specification, Rev. 1.1 (PCI-PM)
PCI Bus Power Management Interface Specification, Revision 1.1, is the only industry specification that ensures compatibility with the power management capabilities of Windows, which uses PME# as the wakeup signal.
The primary PCI bus controller, PCI-to-PCI bridges, devices that implement PME# must comply with the PCI Bus Power Management Interface Specification, Revision 1.1. PCI add-on devices that do not implement PME# must comply with PCI-PM 1.0. See also A4.1.1
B18.104.22.168.1 System provides 3.3 V to all PCI connectors.
System supports 3.3 Vaux if the system supports S3 or S4 states for integrated devices that support waking the system and all PCI slots including MiniPCI.
System support for delivery of 3.3Vaux to the PCI bus must be capable of powering a single PCI slot with 375 mA at 3.3V and it must also be capable of powering each of the other PCI slots on the segment with 20 mA at 3.3V whenever the PCI bus is in the B3 state.
System support for delivery of 3.3Vaux to a PCI bus segment must be capable of powering a single PCI slot on that bus segment with 375 mA at 3.3V and it must also be capable of powering each of the other PCI slots on the segment with 20 mA at 3.3V whenever the PCI bus is in the B3 state.
In the case of systems with multiple PCI bus segments, delivering 3.3Vaux to one PCI bus segment does not mean that all PCI bus segments will be required to implement delivery of 3.3Vaux. However, if a system with multiple PCI bus segments provides 3.3Vaux to one or more segments and not to all segments in the system, these capabilities must be clearly marked and documented so that the end user can determine which slots support this capability. Examples of methods for indicating which slots support 3.3Vaux include icons silk-screened on system board sets, slot color-coding, and chassis icons.
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