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FEE2006 Perugia May 2006

Philippe Farthouat, CERN

SiGe Benefit

            CHIP TECHNOLOGY

FEATURE

 0.25 m CMOS ABCDS/FE

J. Kaplon et al.,

(IEEE Rome Oct 2004)

 IBM enhanced 5HP SiGe

Power: Bias for all but front transistor

330 A

0.8 mW

8*5 A = 40 A (conservative)

0.1 mW 

Power: Front bias for 25 pF load

300 A

0.75 mW

150 A

0.375 mW

Power: Front bias for 7 pF load

120 A

0.3 mW

A

0.13 mW

Total Power (7 pF)        2x1015

                              0.48 mW

Total Power (25 pF)    3x1014

1.1 mW

1.5 mW

0.23mW

Cost and yield (for large area chips) may be a problem

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