hsabaghianb @ kashanu.ac.ir Microprocessors 1-45
Z80 Pin Description
Bus Request (input, active Low).
higher priority than NMI
recognized at the end of the current
forces the CPU address bus, data bus, and MREQ, IORQ, RD, and WR to high-imp.
Bus Acknowledge (output, active,Low)
indicates to the requesting device that address, data, and control signals
MREQ, IORQ, RD, and WR have entered their high-impedance states.