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Signal

Pin

Signal

Pin

Signal

Pin

USBP1-

143

USBP1+

142

USBCLK

146

C/BE0#

198

FRAME#

179

C/BE1#

187

DEVSEL#

184

C/BE2#

178

IRDY#

180

C/BE3#

167

STOP#

185

PIRQA

149

PIRQB

150

PIRQC

151

PIRQD

152

AD21

AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31

USB

172 171 168 166 165 164 163 162 161 160 159

144

-REFRESH

31

T/C

62

OSC

-MEMCS16

70

-IOCS16

71

-MASTER

IOCHK

6

IOCHRDY

18

PHLDA#

110

SERR#

3

TRDY#

181

DRQ5 DRQ6 DRQ7

  • -

    DACK0

  • -

    DACK1

  • -

    DACK2

  • -

    DACK3

  • -

    DACK5

  • -

    DACK6

  • -

    DACK7

RSTISA

91 95 99 85 29 60 21 89 93 97

Motherboard design

129

  • -

    SBHE

  • -

    MEMR

  • -

    MEMW

PIIX3’s functionality includes:

(DD12)

88 90

USBP0-

145

PCI control lines

USBP0+

Enhanced 7-channel DMA with two 8237 controllers. This is supported with the

handshaking lines DRQ0- DRQ7 and

DRQ0

  • DRQ7

.

  • ISA-PCI bridge.

  • Fast IDE support for up to four disk drives (two masters and two slaves). It supports mode 4 timings which gives transfer rates of up to 22 MB/s.

  • I/O APIC (Advanced Programmable Interrupt Controller) support.

  • Implementation of PCI 2.1 which allows for PCI auto-configuration.

  • Incorporates 82C54 timer for system timer, refresh request and speaker output tone.

  • Non-maskable interrupts (NMI).

  • PCI clock speed of 25/33 MHz. Motherboard configurable clock speed (normally 33 MHz).

  • Plug-and-play support with one steerable interrupt line and one programmable chip select. The motherboard interrupt MIRQ0 can be steered to any one of 11 interrupts (IRQ3IRQ7, IRQ9IRQ12, IRQ14 and IRQ15).

  • Steerable PCI interrupts for PCI device plug-and-play. The PCI interrupt lines (PIRQAPIRQD) can be steered to one of 11 interrupts (IRQ3IRQ7, IRQ9IRQ12, IRQ14 and IRQ15).

  • Support for PS/2-type mouse and serial port mouse. IRQ12/M can be enabled for the PS/2-type mouse or disabled for a serial port mouse.

  • Support for 5 ISA slots. Typical applications for ISA include 10 Mbps Ethernet adapter cards, serial/parallel port cards, sound cards, and so on.

  • System Power Management. Allows the system to operate in a low-power state with- out being powered-down. This can be triggered either by a software, hardware or external event. It uses the programmable SMI (system management interrupt) line.

  • Math Co-processor error function. The FERR line goes active (LOW) when a math co-processor error occurs. The PIIX3 device automatically generates an IRQ13 inter- rupt and sets the INTR line (HINT) to the processor. The PXII3 device then sets the

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