X hits on this document

31 views

0 shares

0 downloads

0 comments

5 / 15

130

PC Interfacing, Communications and Windows Programming

IGNNE active and INTR inactive when there is a write to address F0h.

  • Two 82C59 controllers with 14 interrupts. The interrupt lines IRQ1, IRQ3IRQ15 are available (IRQ0 is used by the system time and IRQ2 by the cascaded interrupt line). When an interrupt occurs the PIIX3 uses the HINT line to interrupt the processor.

  • Universal Serial Bus with root hub and two USB ports. With the USB the host con- troller transfers data between the system memory and USB devices. This is achieved by processing data structures set up to by the Host Controller Driver (HCD) software and generating the transaction on USB.

The PCI bus address lines (AD0AD22) connect to the TXC IC and the available interrupt lines at IRQ1, IRQ2IRQ12, IRQ14 and IRQ15 (IRQ0 is generated by the system timer and IRQ2 is the cascaded interrupt line). The PS/2-type mouse uses the IRQ12/M line.

11.4 82438 System Controller (TXC)

The 324-pin TXC BGA (ball grid array) provides an interface between the processor, DRAM and the external busses (such as the PCI, ISA, and so on). Table 11.2 outlines its main pin connections. The TXC’s functionality includes:

  • Supports 50 MHz, 60 MHz and 66 MHz host system bus.

  • Integrated DRAM controller. Supports four CAS lines and eight RAS lines. The memory supports symmetrical and asymmetrical addressing for 1 MB, 2 MB and 4 MB-deep SIMMs and symmetrical addressing for 16 MB-deep SIMMs.

  • Integrated second-level cache controller. Supports up to 512 KB of second-level cache with synchronous pipelined burst SRAM.

  • Dual processor support.

  • Optional parity with 1 parity bit for every 8 bits stored in the DRAM.

  • Optional error checking and correction on DRAM. The ECC mode is software con- figurable and allows for single-bit error correction and multi-bit error detection on single nibbles in DRAM.

  • Swappable memory bank support. This allows memory banks to be swapped-out.

  • PCI 2.1 compliant bus.

  • Supports USB.

The TXC controls the processor cycles for:

  • Second-level cache transfer. The processor directly sends data to the second-level cache and the TXC controls its operation.

  • All other processor cycles. The TXC directs all other processor cycles to their desti- nation (DRAM, PCI or internal TXC configuration space).

11.5 Error detection and correction

Parity or error correction can be configured by software (parity is the default). The ECC mode provides single-error correction, double-error detection and detection of all errors in a single nibble for the DRAM memory.

Document info
Document views31
Page views31
Page last viewedSun Dec 04 21:33:50 UTC 2016
Pages15
Paragraphs1354
Words5176

Comments