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7 / 15

MRASR0#

121

MCASR0#

145

MCASR4#

130

MRASR1#

110

MCASR1#

159

MCASR5#

144

MRASR2#

109

MCASR2#

131

MCASR6#

120

MRASR3#

96

MCASR3#

173

MCASR7#

172

54 284 242 223 211 199 188 162 147 100 79 40 39 18 37 16 55

MAB1

256

MD15

53

MD47

MWE#

235

MD16

262

MD48

259

CCS#

279

TWE#

MD17

264

MD49

MD18

222

MD50

MD19

208

MD51

MD20

200

MD52

MD21

189

MD53

MD22

174

MD54

MD23

148

MD55

MD24

99

MD56

MD25

97

MD57

MD26

78

MD58

MD27

19

MD59

MD28

57

MD60

MD29

17

MD61

MD30

76

MD62

MD31

34

MD63

CBWE#

321

COE#

CGWE#

320

CADV#

BWE

321

132

PC Interfacing, Communications and Windows Programming

Cache address lines

300 CADS#

299

280 GWE#

320

Cache control lines

11.6 PCI interface

The TXC supports up to four PCI busmasters and provides the interface between PCI and main memory. It can operate the PCI interface at 25 MHz, 30 MHz or 33 MHz. When used as a PCI master the PIIX3 runs cycles on behalf of DMA, ISA masters or a bus master IDE.

11.7 82091AA (AIP)

The AIP device integrates the serial ports, parallel ports and floppy disk interfaces. Figure 11.3 shows its connections and Figure 11.4 shows the interconnection between the AIP and the PIIX3 device. The OSC frequency is set to 14.21818 MHz. It can be seen that the range of interrupts for the serial, parallel and floppy disk drive is IRQ3, IRQ4, IRQ5, IRQ6 and IRQ7. Normally the settings are:

  • IRQ3. Secondary serial port (COM2/COM4).

  • IRQ4. Primary serial port (COM1/COM3).

  • IRQ6. Floppy disk controller.

  • IRQ7. Parallel port (LPT1).

Figure 11.4 shows the main connections between the TXC, PIIX3 and the AIP. It can be seen that the AIP uses many of the ISA connections (such as 0WS , IOCHRDY, and so on). The interface between the TXC and the PIIX3 defines the PCI bus and the interface be- tween the PIIX3 and AIP defines some of the ISA signals. It can be seen that the AIP can support up to 8 DMA transfers (DRQ0–DRQ7).

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