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PROCESSOR

Motherboard design

133

-DSKCHG -SIDE1 -RDATA

-WPT -TRK0 -WGATE -WDATA -STEP -DIR -MOTEB -DRVSA -DRVSB -MOTEA -INDEX -DRATE0 -FDDEN

-DTR1 -RI1 -CTS1

-TX1 -RTS1 -RX1 -DSR1 -DCD1

-DTR0 -RI0 -CTS0 -TX0 -RTS0 -RX0 -DSR0 -DCD0

-STR -AutoF

-INTR -SLIN -ERR -ACK BUSY PE

SLCT

D0 D1 D2 D3 D4 D5 D6 D7

74 75 76 77 78 79 80 81 82 83 84 85 86 87 90 89

49 50 48 47 46 45 44 43

41 42 40 39 38 37 36 35

41 42 40 39 38 37 36 35 35

69 67 65 60 58 57 56 55

Floppy disk interface

Secondary serial Primary serial

port interface

port interface

Parallel port interface

82091AA (API)

Address lines

Data lines

ISA handshaking

DMA

Interrupt lines

17 15 12 10

8 7 5 4 3 2 1

32 31 30 29 27 26 25 24

23 22 21 20 19 96 6

100 99 98 97

18 16 13 11 9

33 63

SA10

SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0

SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0

-0WS

IOCHRDY AEN -IOWC -IORC -IO16 TC

DRQ5

-DACK5 DRQ2

-DACK2

IRQ7 IRQ6 IRQ5 IRQ4 IRQ3

RSTDRV X1/OSC

Figure 11.3

API IC.

CTAG[10:0]

HD[63:0]

HA[31:0] HBE#[7:0]

Control

HW/R# HD/C# HM/IO#

MD[63:0] MA[11:2]

SRAM cache

HD[63:0] HA[17:3]

BE#[7:0]

Control

TXC

MAA[1:0] MAB[1:0]

MRAS[4:0] MCAS[7:0] MP[7:0]

DRAM

AD[31:0] C/BE#[3:0] FRAME# TRDY# IRDY# STOP# DEVSEL#

SERR# PHOLD#

PHLDA#

PAR

LOCK#

PCIRST# PIRQ[D:A]

PGNT[3:0] PREQ[3:0]

HINTR HSMI# HSTPC HIGNNG#

PIIX3

LA[23:17] DD[15:0] Control lines

IDE

SA[19:11]

SA[10:0]

SD[15:8]

SD[7:0]

OWS# IOCHRDY AEN XIOW# XIOR# T/C IRQ[15:0] DRQ[7:0] DACK#[7:0] RSTDRV IOCS16#, IOCHK# MEMR#, MEMW# BALE, MEMCS16 REFRESH#, SYSCLK SMEMW#, SMEMR# SMEMR#,

DSKCHG# SIDE1#

Disk drive

FDDEN

RI1# CTS1#

Secondary serial port

DCD1#

RI0# CTS0#

Primary serial port

DCD0#

Parallel port

PD[7:0] STR#

AIP

SLCT

Figure 11.4

Connections between TXC, PIIX3 and AIP.

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