X hits on this document

40 views

0 shares

0 downloads

0 comments

9 / 15

134 PC Interfacing, Communications and Windows Programming

11.8 DRAM interface

The DRAM interface supports from 4 MB to 512 MB with eight row address lines ( MRAS0 MRAS7 ), eight column address lines (MCAS0 MCAS7 ) and a 64-bit data path with 8 parity bits. It can use either a 3.3 V or 5 V power supply and both standard page mode and extended data out (EDO) memory are supported with a mixture of memory sizes for 1 MB, 2 MB and 4 MB-deep SIMMs and symmetrical addressing for 16 MB- deep SIMMs.

Each SIMM (single in-line memory module) has 12 input address lines and has a 32- bit data output. They are normally available with 72 pins (named tabs) on each side. These pins can read the same signal because they are shorted together on the board. For example tab 1 (pin 1) on side A is shorted to tab 1 on side B. Thus the 144 tabs only give 72 useable signal connections.

Figure 11.5 shows how the DRAM memory is organized. It shows banks 1 and 2 (and does not show banks 3 and 4). Each bank has two modules, such that modules 0 and 1 are in bank 1, modules 2 and 3 are in bank 2, and so on. The bank is selected with the MRAS lines; for example, bank 1 is selected with MRAS0 and MRAS1 , bank 1 by MRAS2 and MRAS3 , and so on. An even-numbered module gives the lower 32 bits (MD0MD31) and the odd-numbered modules give the upper 32 bits (MD32MD63). Each module also provides 4 parity bits (MP0MP3 and MP4MP7). Note that the MAA0 and MAA1, and MAB0 and MAB1 signals are the same.

DIMMs (dual in-line memory modules) have independent signal lines on each side of the module and are available with 72 (36 tabs on each side), 88 (44 tabs on each side), 144 (72 tabs on each side), 168 (84 tabs on each side) or 200 tabs (100 tabs on each side). They give greater reliability and density and are used in modern high performance PC servers.

MRAS0

-RAS0

MRAS2

-RAS0

MRAS1

-RAS1

MRAS3

-RAS1

MRAS0

-RAS2

MRAS2

-RAS2

MRAS1

-RAS3

MRAS3

-RAS3

MCAS0

-CAS0

MCAS0

-CAS0

MCAS1

-CAS1

MCAS1

-CAS1

MCAS2

-CAS2

MCAS2

-CAS2

MCAS3

-CAS3

MCAS3

-CAS3

MCAS4

-CAS0

MCAS4

-CAS0

MCAS5

-CAS1

MCAS5

-CAS1

MCAS6

-CAS2

MCAS6

-CAS2

MCAS7

-CAS3

MCAS7

-CAS3

MRAS0

-RAS0

MRAS2

-RAS0

MRAS1

-RAS1

MRAS3

-RAS1

MRAS0

-RAS2

MRAS2

-RAS2

MRAS1

-RAS3

MRAS3

-RAS3

Bank 1

Bank 2

Figure 11.5

DRAM memory interface.

MWE# MAA0-MMA1

Module 1 -W

MD32-MD63

MWE# MAB0-MAB1

MA2-MA11

A0-A1 A2-A11

MP4-P7

MA2-MA11

-W

A0-A1

MD32-MD63

A2-A11

MP4-P7

MWE# MAA0-MAA1

MA2-MA11

Module 0

  • -

    W

A0-A1 A2-A11

Module 3

MD0-MD31

MP0-P3

MWE# MAB0-MAB1 MA2-MA11

Module 2

  • -

    W

MD0-MD31

A0-A1 A2-A11

MP0-P3

Document info
Document views40
Page views40
Page last viewedThu Dec 08 16:30:38 UTC 2016
Pages15
Paragraphs1354
Words5176

Comments