PROTECTION PRODUCTS Applications Information
Device Connection for Protection of Two Data Lines
The STF701 is designed to provide EMI filtering and ESD protection for two I/O lines. The equivalent circuit diagram is shown in Figure 1. The device is connected as follows:
1. Line 1 is connected at pins 1 & 5 and line 2 is connected at pins 3 & 4 (Figure 2). The device is symmetrical so input & output connections can be made on either side of the device. Pin 2 is con- nected to ground. The ground connection should be made directly to the ground plane for best results. The path length is kept as short as pos- sible to reduce the effects of parasitic inductance in the board traces.
Voltage Clamping Characteristics.
The clamping characteristics of the STF701 are opti- mized by the use of two TVS diodes in the protection circuit (Figure 3). An ESD strike on the protected line will be initially suppressed by the first TVS diode. The voltage across the TVS will be the clamping voltage of the device (VC1) given by:
VC1 = Vbr + RD * IPP where Vbr = Breakdown voltage of the TVS RD = Dynamic resistance of the TVS IPP = Peak pulse (ESD) current
The dynamic resistance of the TVS is very small, typically < 0.5.
The second TVS will be subjected to VC1 through the voltage divider formed by the series resistor (R) and the dynamic resistance of the TVS. Since R >> RD then by the voltage divider theorem, the voltage seen by the protected IC will be a few millivolts above the breakdown voltage (Vbr) of the second TVS.
2003 Semtech Corp.
Figure 1 - STF701 Circuit Diagram
Figure 2 - STF701 Connection Diagram
Figure 3 - STF701 Clamping Characteristics