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HP Integrity Superdome architecture

HP Integrity Superdome servers are cache-coherent, non-uniform memory access (ccNUMA) systems. And Integrity Superdome servers present a symmetric multiprocessing (SMP) programming model to the operating system by allowing any processor to have access to any byte of memory anywhere in the system. In fact, it is the first mission-critical UNIX® system to exploit distributed processors and memory. Here’s why.

  • Usable bandwidth scales with system size, thanks to two important design features:

    • HP Integrity Superdome coherency scheme—Unlike some UNIX systems, which rely on snoop- based coherency that results in bottlenecks (large, flat latencies and bandwidth starvation) in high-end configurations, Integrity Superdome servers use a highly customized directory coherency scheme that scales to 16 cells with very low coherency bandwidth overhead.

    • HP Integrity Superdome topology—Integrity Superdome servers implement a point-to-point global packet switch for a communication fabric that is very well balanced across processor, memory, and I/O traffic.

  • Large physical memory with extremely low latency—Integrity Superdome servers support 512 MB, 1 GB, and 2 GB DIMMs, yielding a maximum memory of 1 TB. Even with these high amounts of memory, the latency growth from 2 to 128 processors is only 1.8X (80% growth), which is extremely flat.

  • High I/O bandwidth and connectivity—Integrity Superdome servers provide a high degree of I/O connectivity while preserving bandwidth. There are 192 I/O cards in the system, each with its own dedicated I/O bus; at the adapter level, this aggregates to 64 GB/s of raw bandwidth for PCI and 128 GB/s for PCI-X. The I/O bandwidth available between the system core (processors and memory) and the I/O controllers is roughly 30 GB/s for PCI and 32 GB/s for PCI-X.

  • Large number of high-performance processors—Integrity Superdome servers provide up to 128 Intel Itanium 2 processors—and these are the highest-performance processors in the industry. The system can consist of up to 64 Intel Itanium 2 processors or 64 mx2 Dual-Processor Modules (128 CPUs). The new mx2 Dual-Processor Module enables two Intel Itanium 2 processors sharing a large 32 MB L4 cache to be supported in the same socket that a single Intel Itanium 2 processor would occupy, thus doubling the capacity of the system.

  • True hardware isolation of system resources—Processors, memory, and I/O resources are truly isolated from each other in order to provide flexibility in system usage. This means:

    • The system has great SMP performance to attack large single workloads.

    • Hardware-enforced isolation of resources coupled with great single-system high-availability and manageability features provides a strong consolidation platform.


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