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  • Data buses

  • Optional link to 12 PCI-X I/O slots

Figure 5 illustrates the cell board architecture processors in each socket. The cell has a peak memory bandwidth of 16 GB/s. A connection to a 12-slot PCI-X card cage is optional for each cell, and the peak bandwidth of this link is 2 GB/s. Bandwidth to the crossbar is 8 GB/s per cell.

Error checking and correcting (ECC) exists on all fabric paths, memory paths, and on CPU cache. Parity protection exists on all CPU and I/O links. Single-wire correction exists on fabric and I/O paths.

Figure 5. HP Integrity Superdome cell board and interconnect architecture

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